JPH03196204A - Programmable controller - Google Patents

Abstract

PURPOSE:To process a control program including both bit and word arithmetic instructions by providing a processor exclusive for bit arithmetic instruction processing and a processor capable of the word arithmetic processing. CONSTITUTION:A bit arithmetic processor 12 gives a word arithmetic instruction and an object code to a word arithmetic processor 13 via a word instruction register 11. Therefore the processor 13 can carry out the word arithmetic instructions with synchronization just by searching the register 11 without being conscious of the synchronization. Thus the processor 13 can apply the word arithmetic instruction in a machine language that can be directly carried out and therefore can omit the time to decode the word arithmetic instructions. As a result, the processing speed is increased with a programmable controller.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a programmable controller, and in particular to a programmable controller suitable for rapidly executing instructions in which word operation instructions are mixed in bit operation instructions, and its program execution. The present invention relates to a method, a memory for storing programs, and a method for storing program instructions.

[Conventional technology]

The objects to be controlled by programmable controllers have become more complex in recent years, and PI is included in sequence control.
It has become commonplace to perform D control. For this reason, the control instruction program of the programmable controller is a ladder instruction (bit instruction) that is a sequence instruction.
and numerical operation instructions (word operation instructions).

Conventional programmable controllers that execute a mixture of bit operation instructions and word operation instructions are
For example, as described in Japanese Unexamined Patent Publication No. 56-105505, a configuration may be used in which sequence instructions (bit operation instructions) are processed by hardware and numerical operations (word operation instructions) are processed by a microprogram using a dedicated circuit, or bit In addition to providing a processor that exclusively processes arithmetic instructions, the general-purpose processor that controls the entire programmable controller is configured to also execute word arithmetic instructions.

[Problem to be solved by the invention]

When executing an instruction in which word operation instructions are mixed among bit operation instructions, there is a problem in that the processing takes time. One of the reasons for this is that it takes time to determine which instructions are bit operation instructions and which are word operation instructions. Another cause is that when a general-purpose processor that oversees the operation of the entire programmable controller recognizes and executes a word operation instruction, the word operation instruction is written in a machine language that the processor can execute (
object code), and this translation takes time. The above-mentioned conventional techniques do not solve these problems, and the more complex and large-scale the controlled object, the longer the control process takes, making it impractical. Furthermore, if the sequence commands are executed by hardware, the amount of hardware will increase, which is also impractical.

SUMMARY OF THE INVENTION An object of the present invention is to provide a programmable controller capable of processing instructions in which word operation instructions are mixed in bit operation instructions at high speed, a program execution method thereof, a program instruction storage method, and a memory.

[Means to solve the problem]

The above object is achieved by providing a processor dedicated to processing bit operation instructions and a processor dedicated to processing word operation instructions in addition to a general-purpose processor that controls the entire programmable controller.

For the above purpose, when a processor dedicated to processing bit operation instructions recognizes a word operation instruction and interrupts the processor processing the word operation instruction to cause the processor to execute the word operation instruction, the object memory corresponding to the word operation instruction is This is accomplished by passing code to the processor.

The above object is achieved by adding information identifying whether each component instruction is a bit operation instruction or a word operation instruction when storing instructions to be executed by a programmable controller in a memory.

[For production]

By providing a processor dedicated to processing word operation instructions in addition to the general-purpose processor that controls the entire programmable controller, this dedicated processor is not burdened with processing other than word operation instructions, and processing can be executed at high speed.

In addition, when a processor executes a word operation instruction, a processor dedicated to processing bit operation instructions recognizes the word operation instruction and passes it as an object code when executing the word operation instruction, so that the processor can translate it into machine language. is required, and the processing speed can be increased accordingly.

Yet again. Since each component instruction can be distinguished as a bit operation instruction or a word operation instruction using identification information, it is possible to quickly determine whether the two instructions are the same.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is an overall configuration diagram of a programmable controller according to an embodiment of the present invention. This programmable controller 1 includes a central processing unit (cPU) 2, a sequence processing unit (SPU) 3, and a process input storage memory (PIO memory) 4, and includes a process input/output device (PI○). 5 to motor 6, switch 7,
It is connected to sensor 8 etc.

The central processing unit 2 mainly controls the entire programmable controller 1, and manages each component device 3, 4, etc., executes a communication program, and executes word arithmetic processing other than the machine control program. The sequence arithmetic processing device 3 mainly executes machine control programs such as ladder language. The PIO memory 4 stores the process command value which is the operation result of the sequence operation processing group W3, and periodically reads the on/off state of the process side 6, 7.8 necessary for the operation of the sequence operation processing unit 3. This is used to store the data. In other words, the programmable controller 1 executes calculations based on process data and a control program stored in advance in the sequence calculation processing device 3, and performs on/off control of the motor 6.

FIG. 1 is a detailed configuration diagram of the sequence arithmetic processing device 3. As shown in FIG. The sequence arithmetic processing device 3 has a memory (hereinafter referred to as SEQ memory) 9 that stores a sequence program containing a mixture of bit arithmetic instructions and word arithmetic instructions, and an object code that is a machine language corresponding to each word arithmetic instruction. Memory (hereinafter referred to as OBJ memory)
O, a bit operation processor 12 that exclusively processes bit operation instructions, a word operation processor 13 that exclusively processes word operation instructions of a machine control program (sequence program), and a temporary storage area for object codes taken out from the OBJ memory 10. and a word instruction register 11 for passing this to a word operation processor 13.

FIG. 3 is a diagram illustrating the configuration of the word instruction register 11 and the signal paths within the sequence arithmetic processing device 3. In this embodiment, the word instruction register 11 is composed of an address adder 14 and an object buffer 15.

Note that each signal 9a shown in FIG.

12a, 13a, and 14a will be described later.

FIG. 4 is a diagram showing the storage format of each instruction of the sequence program stored in the SEQ memory 9. As shown in this figure, there is an operation type code B/W indicating whether the instruction is a bit operation instruction or a word operation instruction, an instruction code lN5T indicating the type of instruction, and a parameter PARA.
Configure each command.

FIG. 5 is a program explanatory diagram of the ladder language description 16 in which word operation instructions are mixed in bit operation instructions. Contact symbols and coil symbols are bit operation instructions, and S
UB symbol 17 is a word 5 operation instruction. X0OO, X0OI, ROOI shown in FIG.

ROO2, YOOO, etc. are bit addresses of the PIO memory 4, and RWloo, R11200 are word addresses of the PIO memory 4. The bit operation instructions of such a program are stored in the SEQ memory 9 in the format shown in FIG.

HlooO, Ru2O3) is S in the format shown in Figure 4.
Stored in EQ memory.

In the OBJ memory 10, each word operation instruction in the program is registered in machine language, that is, object code.The object code of the word 5 operation instruction 5UB17 shown in FIG.
It is stored in the area.

When the programmable controller configured as described above executes the program shown in FIG. 5, the bit operation processor sequentially reads instructions from the SEQ memory 9 and performs operations. If a word operation instruction is encountered while sequentially reading bit operation instructions and proceeding with the corresponding control,
The bit operation processor 12 recognizes that it is a word operation instruction from the operation identification code B/W.

The bit operation processor 12, which has recognized that it is a word operation instruction, outputs the address addition permission signal 12a in FIG.
is output to the address adder 14. The address adder 14 receives the instruction code 9a read out from the SEQ memory 9 by the bit operation processor 12 and the address signal 13a from the word operation processor 13, and receives both signals 9a by the address addition permission signal 12a. ,
13a is added.

As a result, the real address where the corresponding object code is stored in the OBJ memory 10 is determined.

FIG. 6 is a diagram showing the relationship between the OBJ memory 10 and the word instruction register 11 during execution of a bit operation instruction. During execution of a bit operation instruction, the address addition permission signal 12a is not output, so the above-mentioned signal 9a and signal 13a are not added, and the address output 1 of the word operation processor 13 is not output.
3a and the real address 14a are the same address. Therefore, as shown in FIG. 6, the first area of the OBJ memory IO is a mapping of the word instruction register 11.

○A jump instruction is given to the first area of BJ memory lO, and the jump destination address is set to word instruction register 1.
If the first address is set to 1, the word operation processor 13 can immediately execute the word operation instruction when the next instruction is a word operation instruction, as described below, by searching the beginning of the register 11. Become. It goes without saying that instead of using the jump instruction, the corresponding object code may be transferred to the register II by switching the address of the BJ memory.

The instruction read by the bit operation processor 12 is the fifth instruction.
In the case of the word operation instruction S U B 17 in the figure, the bit operation processor 12 outputs the address addition enable signal 12a, as described above. As a result, the address adder 14 adds the start address "Me50" in the OBJ memory 10 of the aforementioned object code to the address 13a of the word operation processor 13 based on the instruction code, and as shown in FIG. The object code becomes a mapping of the word instruction register 11. Therefore, the word operation processor 13 can execute a word operation instruction by executing the contents of this register 11.

In a programmable controller that cyclically executes a program containing a mixture of bit operation instructions and word operation instructions, as in the above embodiment, the bit operation instructions and word operation instructions must be executed in the programmed order. This is because the calculation result of the current instruction is used for the calculation of the next instruction. Therefore, it is necessary for the bit operation processor and the word operation processor to execute programs while being synchronized with each other. In the above-mentioned embodiment, the bit operation processor 12 uses the word instruction register 11 to send the word operation instruction to the word operation processor 13 as an object code, so the code operation processor 13 can execute the word operation instruction without being aware of synchronization. By simply searching the register 11, word operation instructions can be executed in synchronization.

According to the embodiment described above, the word operation processor 1
3 is given word operation instructions in machine language that can be executed directly, so there is no time to decode the word operation instructions,
Faster processing is achieved.

Furthermore, when the bit operation processor converts a word operation instruction into an object code, the word operation instruction is executed at the corresponding object code storage address in the OBJ memory, so the word instruction register 11 is configured with only an address adder and a buffer. can. Furthermore, since the word operation instruction included in the bit operation instruction is executed by a dedicated word operation processor,
It is possible to speed up the processing without being bothered by other processing. FIG. 8 is a graph showing the improvement in processing speed when a word operation processor 13 dedicated to machine control is provided. The horizontal axis of this graph shows the proportion of word operation instructions in the control program, and the vertical axis shows the processing time. Note that the horizontal line ■ indicates the processing speed of the general-purpose processor. When bit operation instructions and word operation instructions are both executed by a processor that can process word operations, the processing speed decreases rapidly as the number of word operation instructions increases, as shown by curve ■, and the proportion of word operation instructions decreases. At 10%, the processing speed drops to that of a general-purpose processor. However, as shown in curve ①, by configuring the configuration in which word operation instructions are processed by a dedicated processor and bit operation instructions are processed by a general-purpose processor as in this embodiment, the processing speed of each stage can be increased. . In the case of this embodiment, in addition to this, word operation instructions are given in object code, so even higher speeds can be achieved, and the processing time for word operation instructions is from several tenths to several tenths compared to the conventional interrupt method. It becomes possible to shorten the time by one hundredth.

〔Effect of the invention〕

According to the present invention, there is an effect that a control program containing a mixture of bit operation instructions and word operation instructions can be processed at high speed.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a programmable controller according to an embodiment of the present invention, FIG. 2 is an overall configuration diagram of the programmable controller, and FIG. 3 is a diagram explaining the configuration and signal control of the word instruction register shown in FIG. 1. , Figure 4 is a diagram showing the storage format of instructions, Figure 5 is a diagram showing the control program and SE
A diagram showing the relationship between Q memory and OBJ memory, Figures 6 and 7 are diagrams explaining the relationship between SEQ memory and word instruction register, and Figure 8 is a graph showing performance improvement when a processor dedicated to word operation processing is provided. It is. 1°゛Programmable controller, 2...CPU,
3... Sequence arithmetic processing device, 9... Sequence program (SEQ) memory, 10... Object code (OBJ) memory, 11... Word instruction register, 12... Processor dedicated to bit arithmetic processing, 13...・
- Processor dedicated to word operation processing.

Claims (1)

[Claims] 1. In a programmable controller that executes an instruction in which a word operation instruction is mixed among bit operation instructions, a bit operation that recognizes the word operation instruction and converts the word operation instruction into an object code for word operation processing. A programmable controller comprising: a processor dedicated to processing instructions; and a processor capable of processing word operations, which receives the object code from the processor dedicated to processing bit operations instructions and directly executes the object code. 2. In a programmable controller that executes an instruction in which a word operation instruction is mixed with a bit operation instruction, in addition to the processor that controls the entire programmable controller, there is also a processor that recognizes the word operation instruction and converts the word operation instruction into an object for word operation processing. A programmable controller comprising: a processor for processing bit operation instructions that converts them into code; and a processor dedicated to word operation processing, which receives the object code from the processor dedicated to processing bit operation instructions and directly executes the object code. 3. In a programmable controller that executes an instruction in which a word operation instruction is mixed among bit operation instructions, a memory that stores an object code corresponding to the word operation instruction, a processor capable of processing word operations, and a word operation instruction in the instruction are provided. A programmable controller comprising: a processor dedicated to bit operation instruction processing that recognizes and reads an object code corresponding to the word operation instruction from the memory and passes it to the processor. 4. In a programmable controller that executes an instruction in which a word operation instruction is mixed with a bit operation instruction, a processor that controls the entire programmable controller, a memory that stores an object code corresponding to the word operation instruction, and a processor dedicated to word operation processing. and a processor dedicated to bit operation instruction processing that recognizes a word operation instruction in an instruction, reads an object code corresponding to the word operation instruction from the memory, and passes it to the word operation processing dedicated processor. . 5. In a programmable controller that executes an instruction in which word operation instructions are mixed among bit operation instructions, there is a memory that stores object code corresponding to the word operation instruction, and a memory that stores the object code corresponding to the word operation instruction, and a memory that stores the object code corresponding to the word operation instruction, and when the instruction is a word operation instruction, a memory that stores the object code corresponding to the word operation instruction. a processor dedicated to bit operation processing that recognizes and reads an object code corresponding to the word operation instruction from the memory; a word instruction register that receives the object code read from the memory; and a word instruction register that searches the word instruction register. and a processor capable of word operation processing that reads and executes object code when it is passed from the memory. 6. Provided in a programmable controller that executes an instruction in which a word operation instruction is mixed in a bit operation instruction, in a memory that stores the instruction, a bit is stored in an area for storing each instruction, respectively, to determine whether the instruction is a word operation instruction. A memory for storing program instructions, comprising an area for storing data indicating whether the instruction is an arithmetic instruction. 7. In a memory provided in a programmable controller that executes an instruction in which a word operation instruction is mixed among bit operation instructions and stores said instruction, when each instruction is stored in the memory, it is determined that the instruction is a word operation instruction for each instruction. A method for storing program instructions, characterized in that information is added to identify whether the instruction is a bit operation instruction or a bit operation instruction. 8. In a programmable controller that includes a bit operation processor and a word operation processor and executes an instruction in which a word operation instruction is mixed in the bit operation instruction, the bit operation processor is configured to execute an instruction in which the instruction is a word operation instruction. A program execution method for a programmable controller, characterized in that, in the case of a word operation instruction, an object code corresponding to the word operation instruction is passed to the word operation processor for direct execution. 9. In a programmable controller that includes a bit operation processing processor and a word operation processing processor and executes an instruction in which a word operation instruction is mixed in the bit operation instruction, the word operation processing processor executes a word operation instruction in the instruction. A program execution method for a programmable controller, characterized in that when executing a program, the word operation instruction is received from the bit operation processor and executed in a directly executable object code.