JP2529429B2 - Programmable controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller, and more particularly,
The present invention relates to a programmable controller suitable for high-speed execution of instructions in which word operation instructions are mixed in bit operation instructions.

[Conventional technology]

The controlled object targeted by the programmable controller has become complicated in recent years, and the PI
D control is becoming commonplace. Therefore, the control instruction program of the programmable controller is a ladder instruction (bit instruction) that is a sequence instruction.
And numerical operation instructions (word operation instructions) are mixed.

A conventional programmable controller that executes such an instruction in which bit operation instructions and word operation instructions coexist is such that a sequence instruction (bit operation instruction) is processed by hardware as described in, for example, Japanese Patent Laid-Open No. 56-105505. Arrangement for processing numerical operations (word operation instructions) by a microprogram by a dedicated circuit, or for providing a processor for exclusively processing bit operation instructions and for allowing a general-purpose processor that controls the entire programmable controller to execute word operation instructions I have to.

[Problems to be Solved by the Invention]

When executing an instruction in which word operation instructions are mixed in bit operation instructions, there is a problem in that processing takes time.
One of the causes is that it takes time to determine which of the instructions is a bit operation instruction and which is a word operation instruction. As another cause, when a general-purpose processor that controls the operation of the entire programmable controller recognizes a word operation instruction and executes the word operation instruction, the word operation instruction must be translated into a machine language (object code) executable by the processor. This must be done, and this translation will take time. The above-mentioned conventional techniques do not solve these problems, and the more complicated and large-scale the controlled object, the longer the control process becomes, which is becoming impractical. Further, if the sequence instruction is configured by hardware, the amount of hardware becomes large, which is also not practical.

An object of the present invention is to provide a programmable controller that can process an instruction in which word operation instructions are mixed in bit operation instructions at high speed.

[Means for solving the problem]

In the programmable controller that executes each instruction of a sequence program in which word operation instructions are mixed in bit operation instructions, a first memory storing an object code corresponding to each word operation instruction in the sequence program; In the first memory, the identification information indicating whether each instruction in the sequence program is a bit operation instruction or a word operation instruction and the storage location of the object code corresponding to the word operation instruction in the case of the word operation instruction And a second memory in which the address of the second memory is stored, and each instruction of the second memory is cyclically read, and when the identification information indicates a bit operation instruction, the bit operation instruction is executed, and when it is a word operation instruction, the required instruction is executed. A dedicated processor for bit operation instruction processing to be output and a dedicated processor for bit operation instruction processing A register in which the processor stores the object code reads the corresponding object code from said first memory based on the address corresponding to the word operation instruction when outputting the required instruction,
This is achieved by providing a processor dedicated to word operation instruction processing which searches the register and reads and executes the object code when the object code is stored.

[Action]

When each instruction of the sequence program is stored in the second memory, since identification information indicating whether the instruction is a bit operation instruction or a word operation instruction is added, it is possible to quickly determine both instructions. Become. Moreover, the object code corresponding to each word operation instruction is stored in the first memory, and when the bit operation instruction processing dedicated processor determines that the instruction to be executed is the word operation instruction, the corresponding object code is immediately output from the first memory. Since it is read and passed to the processor dedicated to word operation instruction processing, word operation can be performed at high speed. Furthermore, the word operation instruction processing dedicated processor searches the register itself without receiving the word operation processing instruction from the bit operation instruction processing dedicated processor, and reads and executes the object code when the object code is stored in the register. Therefore, the word operation instruction can be executed in synchronization without being aware of the synchronization with the bit operation instruction processing processor.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is an overall configuration diagram of a programmable controller according to an embodiment of the present invention. The programmable controller 1 comprises a central processing unit (CPU) 2, a sequence processing unit (SPU) 3, and a process input storage memory (PIO memory) 4, and a process input / output unit (PIO) 5 is used. Connected to the motor 6, the switch 7, the sensor 8 and the like.

The central processing unit 2 mainly controls the entire programmable controller 1, manages the respective constituent devices 3 and 4 and executes a communication program, and executes a word operation process other than the machine control program. The sequence operation processing device 3 mainly executes a machine control program such as a ladder language. The PIO memory 4 stores the process command value which is the operation result of the sequence operation processing device 3 and periodically reads the on / off state of the process side 6, 7, 8 necessary for the operation of the sequence operation processing device 3. Stored data. In other words, the programmable controller 1 executes the calculation by the process data and the control program stored in the sequence calculation processing device 3 in advance, and controls the ON / OFF of the motor 6.

FIG. 1 is a detailed configuration diagram of the sequence calculation processing device 3. The sequence operation processing device 3 stores a memory (hereinafter referred to as SEQ memory) 9 in which a sequence program in which bit operation instructions and word operation instructions are mixed is stored, and an object code which is a machine language corresponding to each word operation instruction. Memory (hereinafter referred to as OBJ memory) 10
And a bit operation processor 12 exclusively processing bit operation instructions, a word operation processor 13 exclusively processing word operation instructions of a machine control program (sequence program), and an object code fetched from the OBJ memory 10 temporarily stored. This is a word processor
And a word instruction register 11 to be passed to.

FIG. 3 is a diagram for explaining the configuration of the word instruction register 11 and the signal path in the sequence operation processing device 3. In this embodiment, the word instruction register 11 is an address adder.
It is composed of 14 and an object buffer 15. The signals 9a, 12a, 13a, 14a shown in FIG. 3 will be described later.

FIG. 4 is a diagram showing a storage format of each instruction of the sequence program stored in the SEQ memory 9. As shown in this figure, each instruction is composed of an operation type code B / W indicating whether the instruction is a bit operation instruction or a word operation instruction, an instruction code INST indicating the instruction type, and a parameter PARA. .

FIG. 5 is a program explanatory diagram of the ladder language description 16 in which word operation instructions are mixed in bit operation instructions. Contact symbols and coil symbols are bit operation instructions, and SU
B symbol 17 is a word operation instruction. X00 shown in Fig. 5
0, X001, R001, R002, Y000, etc. are bit addresses of the PIO memory 4, and RW100, RW200 are word addresses of the PIO memory 4. The bit operation instruction of such a program is stored in the SEQ memory 9 in the format shown in FIG.
For UB, the added value 50 and parameters (RW100, H100, RW200) of the word operation instruction are in the format shown in Fig. 4.
Stored in SEQ memory.

In the OBJ memory 10, each word operation instruction in the program is registered in machine language, that is, object code,
The object code of the word operation instruction SUB17 shown in FIG. 5 is stored in the area of the head address "ME50" of the OBJ memory 10.

When the programmable controller having the above-mentioned configuration executes the program shown in FIG. 5, the bit operation processor sequentially reads out the instructions from the SEQ memory 9 and performs the operation. If a word operation instruction is encountered while reading the bit operation instructions sequentially and proceeding with the corresponding control,
The bit operation processor 12 recognizes that it is a word operation instruction by the operation identification code B / W.

Recognizing that it is a word operation instruction, the bit operation processor 12 outputs the address addition permission signal 12a of FIG. 3 to the address adder 14. An instruction code 9a read from the SEQ memory 9 by the bit arithmetic processor 12 and an address signal 13a from the word arithmetic processor 13 are input to the address adder 14, and both signals 9a are generated by the address addition permission signal 12a. , 13a is added. As a result, the real address in which the corresponding object code in the OBJ memory 10 is stored can be obtained.

FIG. 6 is a diagram showing the relationship between the OBJ memory 10 and the word instruction register 11 during execution of the bit operation instruction. Since the address addition permission signal 12a is not output during execution of the bit operation instruction, the above-mentioned addition of the signal 9a and the signal 13a is not performed,
The address output 13a of the word operation processor 13 and the real address 14a are the same address. Therefore, as shown in FIG. 6, the first area of the OBJ memory 10 is a map of the word instruction register 11. A jump instruction is given to the first area of the OBJ memory 10, and when the jump destination address is set to the head address of the word instruction register 11, the word arithmetic processor 13 searches the head of the register 11 to When the instruction is a word operation instruction, the word operation instruction can be immediately executed as described below. It goes without saying that the object code may be transferred to the register 11 by switching the address of the OBJ memory instead of the jump instruction.

The fifth instruction is the one read by the bit arithmetic processor 12
In the case of the word operation instruction SUB17 in the figure, as described above, the bit operation processor 12 causes the address addition enable signal 12a
Is output. As a result, the address adder 14 makes the address 13 of the word arithmetic processor 13 based on the instruction code.
The aforesaid object code, in the OBJ memory 10, is added to the start address "50" of the object code, and the object code becomes a map of the word instruction register 11, as shown in FIG. Therefore, the word operation processor 13 can execute the word operation instruction by executing the contents of the register 11.

In a programmable controller that cyclically executes a program in which bit operation instructions and word operation instructions are mixed, as in the above-described embodiments, the bit operation instructions and word operation instructions must be executed in the programmed order. This is because the operation result of this instruction is used for the operation of the next instruction. Therefore, the bit arithmetic processor and the word arithmetic processor need to execute the program in synchronization with each other. In the above-described embodiment, because the bit arithmetic processor 12 is configured to give a word arithmetic instruction to the word arithmetic processor 13 by using the word instruction register 11,
The word operation processor 13 can execute the word operation instruction in synchronization only by searching the register 11 without being aware of the synchronization.

According to the embodiment described above, the word arithmetic processor
Since 13 is a machine language that can be directly executed and given a word operation instruction, there is no time to decode the word operation instruction,
Higher processing speed is achieved. Further, when the bit operation processor converts the word operation instruction into the object code, the word operation instruction is configured to be executed at the corresponding object code storage address of the OBJ memory.
The word instruction register 11 can be composed of only an address adder and a buffer. Furthermore, since the word operation processor included in the bit operation instructions is executed by the dedicated word operation processor, the processing can be speeded up without being bothered by other processing. FIG. 8 is a graph showing the improvement in processing speed when the word processor 13 dedicated to machine control is provided. The horizontal axis of this graph shows the ratio of word operation instructions in the control program, and the vertical axis shows the processing time. The horizontal line I indicates the processing speed of the general-purpose processor. When both bit operation instructions and word operation instructions are executed by a processor capable of word operation processing, the processing speed sharply slows as the number of word operation instructions increases, as shown in curve II. Will fall to the speed of a general-purpose processor at 10%. However, as shown in the curve III, the word operation instructions are processed by the dedicated processor and the bit operation instructions are processed by the general-purpose processor as in the present embodiment, whereby the processing speed of each stage is increased. . In the case of the present embodiment, in addition to this, a word operation instruction is given by an object code, so that even higher speed can be achieved, and the processing time of the word operation instruction is from several tenths to several tenths as compared with the conventional interrupt method. It will be possible to reduce it to one hundredth.

〔The invention's effect〕

According to the present invention, there is an effect that a control program in which bit operation instructions and word operation instructions are mixed can be processed at high speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a programmable controller according to an embodiment of the present invention, FIG. 2 is an overall configuration diagram of the programmable controller, and FIG. 3 is a diagram for explaining the configuration and signal control of the word instruction register shown in FIG. , FIG. 4 is a diagram showing a storage format of an instruction, and FIG. 5 is a control program and SEQ.
6 and 7 showing the relationship between the memory and the OBJ memory
FIG. 8 is a diagram for explaining the relationship between the SEQ memory and the word instruction register, and FIG. 8 is a graph showing performance improvement when a processor dedicated to word arithmetic processing is provided. 1 ... Programmable controller, 2 ... CPU, 3 ...
… Sequence operation processing device, 9 …… Sequence program (SEQ) memory, 10 …… Object code (OBJ) memory, 11 …… Word instruction register, 12 …… Bit arithmetic processing dedicated processor, 13 …… Word arithmetic processing dedicated processor .

Claims (2)

(57) [Claims] 1. A programmable controller that executes each instruction of a sequence program in which word operation instructions are mixed in bit operation instructions, and a first memory storing an object code corresponding to each word operation instruction in the sequence program, Identification information indicating whether each instruction in the sequence program is a bit operation instruction or a word operation instruction, and in the case of a word operation instruction, the first memory indicating a storage location of an object code corresponding to the word operation instruction A second memory storing an address therein and each instruction of the second memory is cyclically read, and when the identification information indicates a bit operation instruction, the bit operation instruction is executed, and when it is a word operation instruction, a required instruction And a processor dedicated to bit operation instruction processing that outputs When the processor outputs the required instruction, the object code is read from the first memory based on the address corresponding to the word operation instruction, a register for storing the object code, and the object code is stored by searching the register. A programmable controller comprising: a processor dedicated to word operation instruction processing that reads and executes the object code when 2. The programmable controller according to claim 1, further comprising an integrated processor for integrating the entire programmable controller in addition to the bit operation instruction processing dedicated processor and the word operation instruction processing dedicated processor.