JP2784001B2 - Instruction processing circuit of programmable controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an instruction processing circuit of a programmable controller. [Background Art] Recently, high-speed programmable controllers have been demanded, and medium-sized and large-sized models having an execution speed of basic instructions of 1.0 μs or less have been realized. However, because these models achieve high-speed processing by combining bit slices, the cost of high-speed hardware is high, the cost of the entire instruction processing circuit is considerably higher than that of small models, and a balance between cost and performance is achieved. There was a disadvantage that it was not taken. Also, there is an increasing demand for higher speeds for small models with 128 or less I / O points, but there is a problem in terms of cost. [Object of the Invention] The present invention has been made in view of the above problems, and has as its object to provide a low-cost, high-speed instruction processing circuit of a programmable controller. [Disclosure of the Invention] The present invention provides an address generation unit that outputs an address of a user program and an address of a data memory, an instruction fetch unit that stores an instruction read from a program memory and decodes the stored instruction, A data register that stores the read data, a bit ALU part that performs a basic bit operation instruction, a flag part that stores the operation result of the bit ALU part, a timer instruction, a counter instruction, and a 16-bit shift register instruction A gate for an arithmetic execution unit including at least an Acc unit for parallel processing, a word ALU unit for performing subtraction and shift, a subword ALU unit for performing shift and addition dedicated to a timer instruction, and a control clock generation unit for generating a control clock. In the case of a differential instruction in the instruction processing circuit of a programmable controller composed of an array, Apart from the 16-bit data bus connected instruction in a program memory storing the results of the previous scan in a first clock, 1 bit RAM by bit en
, And the flag of the operation result of the current scan is stored in the 1-bit RAM by the second clock.
And the operation result is set in the flag section at the falling edge of the second clock. Hereinafter, the present invention will be described with reference to examples. FIG. 1 shows a circuit configuration of an embodiment of the present invention which can be formed into a gate array with about 2500 gates including other peripheral circuits.
An address generation unit A, an instruction fetch unit B, an operation execution unit C, and a CPU command register D constituting other parts
And a control clock generator E and the like. The address generator A includes a program counter 1 and a data real address unit 2. The program counter 1 is constituted by a binary counter and outputs an address of a program memory (not shown) storing a user program. The data real address unit 2 outputs an address of a data memory (not shown) by a combination of an instruction decoder signal and a clock state. The instruction fetch unit includes an instruction register 3 and an instruction decoding unit 4. The instruction register 3 is a register for reading and storing an instruction from the program memory, and the instruction decoding unit 4 stores the instruction stored in the instruction register 3. The decoding is performed, and signals are output to the address generation unit A, the control clock generation unit D, and the operation execution unit C. The operation execution unit C includes a data register 5, a bit ALU6,
Flag section 7, OUTL / A section 8, operation status register 9, Acc section 10, wALU section (word ALU section) 11, swAL
The data register 5 includes a U section (subword ALU section) 12, an R register 13, and a time base clock counter (BCNT) 14, 15. The data register 5 stores contact data read from the data memory in 16-bit units. The bit ALU unit 6 constitutes an operation unit of a 1-bit logical operation instruction, and stores an operation result in the flag unit 7. Flag section 7
Is an operation result flag register composed of 16 bits, and performs an operation in combination with the bit ALU unit 6. OUTL ・
The A unit 8 is a logic unit that operates contact data according to the values of the data register 5 and the flag unit 7 when executing an output instruction such as an OUT instruction or a Keep instruction. Further, when executing the timer instruction, the counter instruction, and the shift register instruction, the arithmetic status register 9 transfers the contents of the flag unit 7 of the previous scan to the Acc unit 10, and stores the contents of the Acc unit 10 and the contents of the flag unit 7 immediately before. Is a register that stores operation modes of reset, hold, and operation in the combination of. The Acc unit 10 is a 16-bit accumulator for executing a timer instruction, a counter instruction, and a shift register instruction, and realizes functions such as transfer, shift, and subtraction in combination with the wALU unit 11. The wALU unit 11 is a logic unit that realizes functions such as transfer, shift, and subtraction in combination with the Acc unit 10. swAL
The U unit 12 is an arithmetic logic unit dedicated to a timer instruction, and realizes functions such as addition, shift, and transfer in combination with the R register 13 and the BCNTs 14 and 15. R register 13 is swAL
Transfer from BCNTs 14 and 15 and BCNT
The contents are also used for a subtraction function with the Acc unit 10 via the wALU unit 11 for realizing an addition and shift function with 14, 14. BCNTs 14 and 15 are registers for storing timer instructions, for example, values corresponding to reference clocks of 10 msec and 100 msec, respectively, when the timer instruction is executed. The CPU command register D specifies the operation mode of the entire instruction processing circuit, and can specify a one-step operation, a breakpoint function, and the like. The control clock generator E generates a control signal required for the instruction processing circuit based on the basic clock CLK. The control clock generator E includes clocks CK1, CK2, CK3 required for the operation shown in FIG. Is provided with a reference clock generation circuit 16 for generating the data. The reference clock generating circuit 16 generates the clocks CK1, CK2, and CK3 by inputting the basic clock CLK to the ternary counter 16a. The clock CK1 is a fetch clock of an instruction, and the clock CK2 is a data load or a flag ( The clock CK2 is used to perform a 1-bit process of a basic instruction such as START or AND using the bit ALU unit 6 and the flag unit 7. Then, in the case of a differential instruction, the result of the previous scan is clocked by the clock CK1, and the RA constituting the program memory storing the instruction is used.
Separate from the 16-bit data buses D _{0 to} D ₁₅ connected to M, a 1-bit dedicated bus SD is used to load data from a 1-bit RAM, and the clock CK2 is used to set the flag of the current scan operation result from the 1-bit RAM. The result is stored in the data memory, and the operation result is set in the flag section 7 at the fall of the clock CK2. Next, the operation of the instruction processing circuit of the present invention will be described based on the time charts of FIGS. First, FIG. 3 is an execution time chart of a basic instruction of START and AND, and FIG. 3A shows a basic clock CLK,
Based on the basic clock CLK, the control clock generator E
As a result, an AEN (address enable) signal shown in FIG. 4B is generated, and the circuit of the present invention is switched to the active state. In other words, AE
The N signal is a signal for switching between the active state and the passive state of the circuit of the present invention in a hardware manner. And is a chip select signal shown in FIG. (I) (j) ▲ ▼ signals, ▲ ▼ signal generated from the control clock generating section E, RAM and 1 bit is connected to the 16-bit data bus D ₀ to D ₁₅ 1 connected to dedicated bus SD
Bit RAM is chip-selected, and ▲ in FIG.
▼ Address output of program counter 1 by signal
Select is output as shown in FIG. (P) to the address bus A ₁ to A ₁₅ in. Then, an instruction from the program memory is stored in the instruction register 3 by an OPCK signal which is a latch clock signal shown in (g) of FIG. 7 (g) created by combining the AEN signal and the clock CK1 of FIG. q), the instruction is decoded by the instruction decoding unit 4, and a signal based on the decoding is output to the address generation unit A, the control clock generation unit E, and the operation execution unit C. Then, at the falling edge of the OPCK signal, the signal ▲ shown in FIG. 9 (o) is applied to the data real address section 2 to select the address b of the data memory and output it to the address buses A _{1 to} A ₁₅ . With this address output, the contact data (DATA) is taken into the data register 5 from the data memory,
Then, the operation is performed by the bit ALU unit 6 and the flag unit 7. This timing is the period shown in FIG.
The calculation result is stored in the flag section 7 at the time of the falling edge of the clock CK2 shown in FIG. In the middle of this period, the PCiNC signal shown in FIG. 7 (m) is supplied to the program counter 1, and the value of the program counter 1 is incremented at the time of its rise. Here, the address is in the form of PC ← PC + 2 because A ₀ is fixed at “L”. Then, the reset is applied at the falling edge of the clock CK3 shown in FIG. 9E, and the execution of the operation is terminated at this point. The pulse width of the clock CK3 is short because the ternary counter 16a of the reference clock generation circuit 16 is reset by the reset signal REST. By the way, the sync signal shown in FIG. 3 (f) is a clock indicating the beginning of a machine cycle, and this clock generation period T is the instruction execution time T. For example, when the reference clock CLK is 5 MHz
If so, the instruction execution time T is 0.4 μs, and if it is 4 MHz, it is 0.5 μs. Also, (k) and (l) in FIG.
▼, write signal ▲ ▼. Next, the processing of the differential instruction will be described with reference to the execution time chart of FIG. (A) to (g) and (i) to (q) in FIG. 4 correspond to (a) to (g) and (i) to (q) in FIG.
To perform the processing of this instruction, the address output of the program counter 1 is selected by the signal ▼, the address a is output to the address buses A _{1 to} A ₁₅ , and the operation result of the previous scan is output to the 1-bit RAM at the clock CK 1. In the clock CK2, the value of the operation result flag of the current scan is stored in the 1-bit RAM (period in FIG. 4 (h)), and the operation result is set in the flag section 7 at the falling edge of the clock CK2. is there. FIG. 5 shows an execution time chart when each instruction processing of the timer, the counter, and the shift register is performed. As shown in FIG. 5A, the interval of the sync signal, that is, the instruction execution time T is shown in FIG. ) Corresponds to 10 reference clocks CLK, and 2.0 μs if the reference clock CLK is 5 MHz. For these instructions, the reference generation clock circuit 16 shown in FIG. 2 uses the clocks CK1, CK2 and CK3 shown in FIGS. 5 (d), (e) and (f) as well as FIG. (H) φ ₁ shown
And a φ ₂ phase clock, and the φ ₁ clock is used as the clock input of the machine state counter 16b, and the clock φ ₂
The control clock is generated by combining the output of the machine state counter 16b shown in FIG. And Acc part 1
Subtraction, counting, and right shift are performed centering on 0 and the wALU unit 11, and in the case of a timer instruction in particular, auxiliary calculations are performed in parallel by the swALU unit 12 and the R register 13. Thus, the instruction fetch is performed by the OPCK signal shown in FIG. 5J created by combining the AEN signal shown in FIG. 5C and the clock CK1 shown in FIG. In the case of the status fetch shown in (k), the operation result flag of the previous scan is transferred from the operation status register 9 to the Acc section 10 by the Acc ▼ signal shown in FIG. ▼ The value of BCNT 1415 is transferred to the R register 13 by the signal. Next, the contact data is stored in the data register 5 by the data load shown in FIG. 1 (l), and the operation condition is then set by the operation result flag and the Acc unit 10 based on the status operation clock of FIG. Then, the result is stored in the operation status register 9. The processing in the subsequent states differs depending on the result. Processing such as shift, subtraction, and increment is shown in FIG.
The 16-bit operation is performed by the AccCLK signal shown in (1). In the case of a timer instruction, the TMP1 signal shown in (r)
Is added to the R register 13, the result is stored in the R register 13, and the R register 13 is latched by the latch signal shown in FIG. Shift 13 by 2. At this time, the current value or the set value is transferred to the Acc unit 10. Then, the value of the R register 13 is subtracted by the Acc section 10 according to the AccCLK signal shown in FIG. In addition, the output of the Acc section 10 is enabled by the Acc ▼ signal of FIG. The signal ▲ in FIG. 5 (u) is a clock for outputting the operation result flag of the current scan to the status area of the timer and the counter.
The signal is a clock for operating and outputting the contact data by the bit ALU unit 6. In addition, FIG.
▼ signal, FIG. (X) shows ▲ ▼ signal, FIG. (Y) shows ▲ ▼ signal, and FIG.
▼ Each signal is shown. FIG. 2 (a) shows the PCiNC signals. In addition, the INTCLK signal shown in Fig. (Β) detects an interrupt or an extension instruction at the end of instruction execution, and if these signals are present, the AEN signal is switched from “H” to “L” after execution of the instruction is completed. , Signals for setting the circuit of the present invention to a passive state. [Effects of the Invention] The present invention is configured as described above, and is provided with a dedicated arithmetic circuit for executing each instruction such as a bit operation instruction, a differentiation instruction, a timer instruction, and a counter instruction. , Each instruction can be executed, and the instruction processing can be performed at high speed. Even with built-in peripheral circuits, the number of gates can be reduced, and since it can be configured with two components, a gate array and a memory, costs can be reduced and a 16-bit CPU and multiprocessor configuration can be easily realized. It works. In the case of a differential instruction, the result of the previous scan is loaded from the data memory consisting of 1-bit RAM by the first clock, separately from the 16-beat data bus connected to the program memory storing the instruction. Then, the flag of the operation result of the current scan is stored in the data memory consisting of the 1-bit RAM by the second clock, and the operation result is set in the flag section at the falling edge of the second clock. By using a 17-bit configuration in which 1 bit is added to 16-bit data instead of 16-bit data, there is an effect that the restriction on the use of the differential instruction is eliminated, and the high-speed processing can be achieved with the shortest 2 cycles.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is a specific circuit diagram of a basic clock generation circuit used in the embodiment, and FIGS.
FIG. 5 and FIG. 5 are time charts for explaining the operation of the above. A: Address generation unit, B: Instruction fetch unit, C:
Arithmetic execution unit, E: control clock generation unit, 1: program counter, 2: data actual address unit, 3: instruction register, 4: instruction decode unit, 6: bit ALU
Section, 7 ... Flag section, 10 ... Acc section, 11 ... wALU section, 12
...... This is the swALU part.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁶ , DB name) G05B 19/00-19/05

Claims (1)

(57) [Claims] An address generation unit that outputs an address of a user program and an address of a data memory; an instruction fetch unit that stores an instruction read from the program memory and decodes the stored instruction; and stores data read from the data memory. A data register, a bit ALU part for calculating a basic bit operation instruction, a flag part for storing the operation result of the bit ALU part, a timer instruction, a counter instruction,
Acc for 16-bit parallel processing of shift register instructions
Programmable controller configured with a gate array including at least an arithmetic execution unit including a unit, a word ALU unit that performs subtraction and shift, a subword ALU unit that performs shift and addition dedicated to a timer instruction, and a control clock generation unit that generates a control clock In the case of a differential instruction, the instruction processing circuit is connected to a program memory storing the instruction.
Separately from the 16-bit data bus, the result of the previous scan is loaded from the data memory consisting of a 1-bit RAM by the first clock using the first clock, and the flag of the operation result of the current scan is loaded by the second clock using the 1-bit flag. An instruction processing circuit for a programmable controller, wherein the instruction processing circuit is stored in a data memory composed of a RAM and sets an operation result in a flag section at a falling edge of a second clock.