JPS6133721Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a control device using a microprocessor, which generates a pulse width signal having an arbitrary integral multiple of the period of an internal clock.

(Prior Art) When applying a control signal from a microprocessor operating according to a high-speed internal clock to a relatively low-speed input/output device (I/O), it is necessary to use a pulse width signal that is an integral multiple of the internal clock. need to be created. In such cases, conventionally, a counter has been used to count the internal clock and decode it to obtain a desired pulse width signal.

(Problems to be Solved by the Invention) However, the device configured in this manner requires a counter and a decoder in addition to the microprocessor, so it has the disadvantage of increasing the amount of hardware used. Since microprocessors have a wealth of functions, it is desirable to utilize these functions as much as possible to reduce the amount of hardware used.

An object of the present invention is to provide a device that generates a pulse width signal having an arbitrary integral multiple of the period of the internal clock of a microprocessor without using a counter, and that facilitates synchronization with a microprogram. .

(Means for solving the problem) The present invention which achieves the above purpose sets the bits of the ROM in which the microprogram is stored, from the part corresponding to the rising edge of the pulse to the part corresponding to the falling edge, and at the rear end to "1". The microprogram has an internal register in which a bit pattern in which one bit pattern and the other is set to "0" is written by the microprogram, and a shift register that outputs the bit pattern set in this internal register bit serially according to the microprogram. a first clock outputting a clock for reading and executing a microprogram stored in the ROM, and a second clock outputting a clock for shifting by the shift register, and the shift register starts bit shifting. a clock generation circuit that stops the output of the first clock and outputs the first clock to the microprocessor again after inputting a looping release pulse; A first flip-flop generates a pulse width signal corresponding to the bit pattern set in the internal register, and a pulse width signal output of this first flip-flop is input. A second flip-flop detects the fall of the pulse width signal, and a logical operation is performed between the signal from the second flip-flop and the signal output from the shift register, and after the fall of the pulse width signal, the bit at the rear end is detected. and a gate that outputs the looping release pulse at the time of input.

(Operation) The microprocessor decodes the microprogram and serially outputs the bit pattern via the shift register. The first flip-flop generates a pulse having a period corresponding to the second clock in response to the serial output signal.

The second flip-flop and gate signal to the clock generation circuit that the pulse generation is finished. The clock generation circuit resumes the operation of the microprocessor that had been stopped during pulse generation.

(Embodiment) FIG. 1 is a conceptual block diagram of an embodiment of the present invention.
In FIG. 1, 1 is a register and arithmetic logic unit (hereinafter referred to as RALU), 2 is a RALU control section, 3 is a clock generation circuit, 4 is a go-pulse generation circuit, 5 is an input bus, and 6 is a clock generation circuit.
is the output bus.

RALU1 is general and random
Access memory (RAM) 11, Q register 1
2. It consists of a RAM shift unit 13, a Q shift unit 14, an arithmetic logic unit (ALU) 15, and switchers 16 and 17 provided on the input and output sides thereof.

The RALU control unit 2 is also a general one, and includes a read-only memory (ROM) 21, a ROM data register 22, and an address selector 23.
and a ROM address register 24.

A micro program is stored in the ROM21, and each instruction of the micro program is
It is read out according to the address set in the ROM address register 24, its data part is given to the ROM data register 22, and its address part is given to the address selector 22. Data is set in the ROM data register 22 in synchronization with the data set clock DSC of the clock generation circuit 3, and each field is set as a RALU.
control signal, RALU data signal, I/O control signal,
and output as a go gate control signal. The address selector 23 switches between the address signal given from the ROM 21 and the address signal given from the RALU1, and selects the address signal given from the ROM address register 2.
Give to 4. An address is set in the ROM address register 24 in synchronization with the data set clock DSC. Therefore, microinstructions are sent to the ROM one after another according to the data set clock DSC.
The data is read from the ROM data register 22 and output to each section.

The RALU 1 processes data given from the micro program control unit 2 or I/O (not shown) via the input bus 5 according to the micro program, and the result is sent to the micro program control unit 2 or I/O via the output bus 6. /Give to O. RALU
1 Q shift unit 14 terminal digit output signal
Qm is given to the go pulse generation circuit 4.
RALU 1 operates in synchronization with the opposite phase clock of clock generation circuit 3 (clock signal path omitted).

The go pulse generation circuit 4 is the Q shift of RALU1.
The output signal Qm of the unit 14 and the RALU control section 2
It operates based on the go gate control signal of the ROM data register 22, and the data set clock
Generates a go pulse with a pulse width that is an integral multiple of the DSC period. The go pulse is given to the I/O as a signal indicating the significant period of the I/O control signal.
The I/O operates according to the contents of the I/O control signal at the time when the go pulse is generated. The go pulse needs to have an appropriate pulse width.

A detailed configuration of the go pulse generation circuit 4 is shown in FIG. In Fig. 2, 41 and 42 are JK flip-flop circuits, and 43 is a D-type flip-flop circuit.
The flop circuit includes an inverter 44 and an AND gate 45. JK flip-flop circuit 41
The output signal Qm of the Q shift unit 14 is applied to the J terminal and the K terminal in positive phase and the opposite phase, respectively, and the data set clock of the opposite phase of the clock generation circuit 3 is applied to the CP terminal. The Q output of the JK flip-flop circuit 41 is output to the I/O as a go pulse, and
The signal is applied to the JK flip-flop circuit 42 at the CP terminal. The JK flip-flop circuit 42 is
The terminal is connected to a "1" level potential point, the K terminal is connected to a "0" level potential point, and the Q terminal is connected to one input terminal of an AND gate 45. The output signal Qm of the Q shift unit 14 is applied to the other input terminal of the AND gate 45. The output signal of AND gate 45 is applied to clock generation circuit 3 as a looping release signal.

The D type flip-flop circuit 43 is
A “0” level signal is given to the terminal, a looping signal of the clock generation circuit 3 is given to the CP terminal, and a ROM data signal is given to the S terminal.
Go gate control signal GO GATE of register 22
(r) is applied, and an on-power clamp signal is applied to the R terminal from an on-power clamp circuit (not shown). Here, the looping signal is a signal that temporarily stops the output of the clock DSC of the clock generation circuit 3 and keeps the microprogram in a wait state. The Q output of the D type flip-flop circuit 43 is applied to the R terminals of the JK flip-flop circuits 41 and 42 as a go gate signal.

In the device configured as described above, the operation when generating a go pulse is as follows. An explanatory diagram of the operation is shown in FIG. Prior to the generation of the go pulse, RAM11 is
A pulse designation signal having a bit pattern corresponding to the go pulse is written into one of the registers AUX ₀ and Q register 12. Assuming that the bit pattern data is 16 bits and the capacity of register AUX ₀ and Q register 12 is 8 bits each, the first half of the bit pattern is written to register AUX ₀ , and the second half is written to Q register 12. written. The bit pattern is such that "1" continues from a portion corresponding to the rising edge of the go pulse to a portion corresponding to the falling edge, and is "0" in the other portions. By arbitrarily selecting the bit positions of the rising and falling parts when determining the bit pattern, the phase and pulse width of the go pulse can be arbitrarily determined. However, MSB
(most significant bit) is always set to "1" to make the rear end of the bit pattern clear.

The bit patterns written to register AUX ₀ and Q register 12 are concatenated right shifted in RAM shift unit 13 and Q shift unit 14 by microinstructions. Shifting is accomplished by anti-phase data set clocks. When the shift starts, the clock generation circuit 3 stops the data set clock DSC, puts the microprogram in a wait state, and sets the looping signal to "0". At this time, the go-gate control signal () generated from the ROM data register 22 also becomes "0", so the D-type flip-flop circuit 43 is set, and the go-gate signal GC GATE becomes "1". .

When the bit pattern is shifted, each bit of the bit pattern is serially output from the last digit of the Q shift unit 14 starting from the LSB. This serial signal is sent to the go pulse generation circuit 4.
It is applied to the JK flip-flop circuit 41 and is set by a data set clock of opposite phase. Assuming that the bit pattern is now as shown in Figure 3, the 4 bits from the LSB are "0", so the JK flip-flop circuit 41
The Q output of is set to "0" during four cycles of the clock. Since the 5th bit continues to be ``1'' for 7 bits, the Q output remains ``1'' during the 7 cycles of the clock, and a go pulse is generated. From then on, since the bit pattern becomes "0", the Q output also becomes "0", and the generation of the go pulse ends.

When the Q output becomes "0", the JK flip-flop circuit 42 is set, and its Q output becomes "1", opening the AND gate 45.
Therefore, the trailing edge of the bit pattern comes and the MSB
“1” is J of JK flip-flop circuit 41
When applied to the terminal, this is the AND gate 4
5 and is applied to the clock generation circuit 3 as a LOOPING release signal. This allows the bit
When the pattern shift is completed, the wait state of the microprogram is cleared and the microprogram moves to the next step. In other words, micro
The processor generates one go pulse with a predetermined pulse width and moves on to the next data processing. Since the looping is released, the D type flip-flop circuit 43 is reset, thereby
JK flip-flop circuits 41 and 42 are also reset.

(Effects of the invention) As explained above, the invention has the following effects.

(A) Since the pulse width signal is generated using the JK flip-flop circuit 41 and the clock generation circuit 3, a counter or decoder is not required, and the amount of hardware used is small.

(B) Internal registers (RAM11 and Q register 1
Since the pulse width signal is generated according to the bit pattern of 2), the pulse width and phase of the pulse width signal can be changed only by changing the contents of the internal register.

(C) While the pulse width signal is being transmitted, the microprogram is placed in a wait state by the clock generation circuit 3, and after the pulse width signal is being transmitted, the wait state is released by the JK flip-flop 42 and the gate 45. Easy to synchronize with microprograms.

(D) The clock generation circuit 3 is based on a stable oscillator such as a crystal, and uses the clock generated by this to generate a pulse width signal, so it can generate a more accurate time width than a monostable multivibrator etc. I get a signal.

[Brief explanation of the drawing]

FIG. 1 is a conceptual block diagram of an embodiment of the present invention, FIG. 2 is a detailed diagram of a part of the apparatus shown in FIG. 1, and FIG. 3 is an explanatory diagram of the operation of the apparatus shown in FIG. 1. 1...Register and arithmetic
Logic unit (RALU), 11... Random access memory (RAM), 12... Q register, 13, 14... Shift register, 15
...Arithmetic logic unit (ALU), 16,17...Switcher, 2...RALU
Controller, 21... Read only memory (ROM), 22... ROM data register, 23
...Address selector, 24...ROM address register, 3...Clock generation circuit, 4...
Go pulse generation circuit.

Claims (1)

[Claim for Utility Model Registration] A ROM in which a microprogram is stored has a bit pattern in which the bits from the rising edge to the falling edge of the pulse and at the rear end are set to "1" and the other bits are set to "0". a microprocessor having an internal register written in by the microprogram, a shift register that outputs the bit pattern set in the internal register bit-serially according to the microprogram; and a microprogram stored in the ROM. a first clock outputting a clock for reading and executing a bit; a second clock outputting a clock for shifting by the shift register; a clock generation circuit that outputs the first clock to the microprocessor again after inputting the looping release pulse; and a clock generation circuit that inputs the signal output from the shift register and a second clock generated by the clock generation circuit, and A first flip-flop generates a pulse width signal corresponding to a bit pattern set in a register, and a second flip-flop receives the pulse width signal output of the first flip-flop and detects the falling edge of this pulse. , performs a logical operation on the signal from the second flip-flop and the signal output from the shift register, and outputs the looping release pulse when the rear end bit is input after the fall of the pulse width signal. 1. A pulse width signal generator comprising a gate.