JPS6368924A - System for controlling data processing of microprocessor - Google Patents

Abstract

PURPOSE:To improve the data throughput of a system by providing a data register in the microprocessor, selecting an external register only in a 1st cycle among arithmetic processing cycles, and setting the data in the data register and releasing and holding the external register ready for external access. CONSTITUTION:An internal register 11 and an arithmetic means 12 are provided in the microprocessor 10 and arithmetic between data of the register 11 and external register 20 is carried out to process the data. In this constitution, the data register 13 is added newly in the processor 10 and connected to the arithmetic means 12, and data read out of the external register 20 is set in the register 13. Consequently, the register 20 is selected only in the 1st cycle among arithmetic processing cycles and data is read out and inputted to the register 13. In the next cycle, the means 12 performs arithmetic processing between data of the registers 13 and 11 to improve the data throughput of the whole system.

Description

[Detailed Description of the Invention] [Summary] In a data processing control method for an MPU when performing an operation between data in a register inside the MPU and an external register, a data register is provided in the MPU and the operation is performed. Select the external register for the first cycle of the processing cycle, set the data in the data register, release the external register from MP[J to make it accessible from the outside, and then set the data in the data register in the next cycle. Read and perform calculations. Thereby, the data processing efficiency of the entire system can be improved and the circuit configuration can be simplified.

[Industrial application field]

The present invention provides a data processing control method for a microprocessor;
In particular, the present invention relates to a data processing control method when performing an operation between data in a register outside a microprocessor and data in a register inside the microprocessor.

[Conventional technology]

In a microprocessor, in addition to arithmetic processing between data stored in internal registers, arithmetic processing is performed between data in registers external to the microprocessor and data in internal registers of the microprocessor.

FIG. 4 is a block diagram showing a conventional microprocessor data processing control method for data in external registers.

In FIG. 4, 30 is a one-chip microprocessor (MPU), and 40 is an external register.

In the MPU 30, 31 is a general-purpose internal register in which data to be operated and operation results are stored. 32 is an A bus multiplexer (A bus MPX), and internal register 3
1, input data from another calculation section (not shown), and input data from the external register 40.

33 is a B bus multiplexer (B bus MPX) which selects one of input data from the internal register 31 and other arithmetic units. 34 is an arithmetic unit (ALU), which is connected to the A bus MP.
Performs calculations between data input from X32 and B bus MPX33. 35 is an external register select circuit (XR3
EL circuit) generates an external register select signal (XR3EL signal) that selects the external register 40. 3
6 is an external register address register (XRAD register) in which an external register address (XR address) for accessing the external register 40 is set.

41 is an external register multiplexer (XRMPX),
One of the input data from the arithmetic unit 34 of the MPU 30 and the input data from external hardware (not shown) is selected and stored in a predetermined location of the external register 40.

Next, the operation of FIG. 4 will be explained with reference to the operation timing chart of FIG. 5.

In FIG. 5, CK+, CKt, etc. are clocks for MPU control, and between clocks CK and CK, between CKt and C
One cycle is formed between K1, etc. (Fig. 5 (a)
)).

During two cycles from the falling time t of the clock CKI to the falling time t3 of the clock CK, the MPU 3
Arithmetic processing is performed at 0 (FIG. 5(b)). At the same time, the XR3EL circuit 35 generates an XR3EL signal,
The external register 41 is selected during two cycle periods of t and xjs (FIG. 5(C)). During the two cycle period from t1 to t selected by the XR3EL signal,
No one other than the MPU 30 can access the external register 41.

When the internal register 31 is accessed at the falling time t1 of the clock CK, the read data is sent to the B bus MPX33 (FIG. 5(e)).

On the other hand, at the falling time t1 of the clock CK, XR3
When the EL signal is generated, the address is read from the XRAD register 36 and the external register 40 is accessed. Since there are many MPUs (not shown) in addition to the MPU 30, reading data from the external register 40 requires
This is done faster than reading the internal register (Figure 5c).
d)).

In the latter half of the cycle (tg"tz), the A bus MPX
32 selects the data of the external register 40 and transfers it to the B bus MP.
X33 selects the data in internal register 31 and sends it to ALU3.
Add to 4.

When the predetermined calculation is completed in the ALU 34 (Fig. 5 (
f)) In the next cycle, the operation result is stored in a predetermined location of the external register 40 via the internal register 31 or the XRMPX 41 (FIG. 5 (phantom)).

By repeating the above processing, calculations are performed in units of two cycles.

[Problems to be Solved by the Invention] As described above, in the conventional data processing control system of a microprocessor, calculations are performed in units of two cycles, during which time the external register 40 is selected by the MPU 30. During the two cycle period selected by the MPU 30, external hardware such as peripheral devices cannot access the external register 31 and is forced to wait.

For this reason, there is a problem in that the data processing efficiency of the entire system including external peripheral devices is reduced.

Furthermore, if the external register 40 is accessed from the outside and data is written during the second half cycle (tz to ts) when the MPU 30 is performing arithmetic processing, there is a risk that the contents of the data read by the MPU 30 may be changed. be. For this reason, there is a problem in that a special hardware circuit must be provided to prohibit access from the outside not only during the first half cycle but also during the second half cycle.

The present invention selects the external register 40 only in the first cycle during the processing cycle period when the MPU 30 performs an operation, and releases the external register 40 from the MPU 30 in the subsequent processing cycles so that it can be accessed from the outside. It is an object of the present invention to provide a data processing control method for a microprocessor that improves the data processing efficiency of the entire system and eliminates the need for a special circuit that prohibits data writing to an external register 40 from the outside.

[Means for solving problems]

The solution taken by the present invention will be explained with reference to FIG. FIG. 1 is a diagram explaining the principle of the present invention.

In Figure 1, 10 is a microprocessor (MPU)
and 20 is an external register.

In MPU10, 11 is an internal register in which calculation data is stored. 12 is an arithmetic means that performs arithmetic processing on input data.

The XR3EL signal is a signal that selects the external register 20, and is supplied from MPU10 or from outside of MPU10. The XR address is an address for accessing the external register 20, and is supplied from outside MPU10 or MPtJlo.

Reference numeral 13 denotes a data register, into which data read from the external register 20 is set. The data read from the data register 13 is supplied to the calculation means 12. Note that an existing register in MPU10 may be used as this data register.

[For production]

The operation of FIG. 1 will be explained with reference to the operation timing chart of FIG. 2.

In FIG. 2, CKI, CF2, etc. are clocks for MPU control, and adjacent clocks form one cital (FIG. 2(a)).

The MPU10 performs predetermined arithmetic processing during two cycles from the falling time t1 of the clock CK+ to the falling time t of the clock CK3 (FIG. 2(b)). Note that these two cycles may be two cycles between the rising points of the clocks CKI and CKff.

On the other hand, the XR3EL signal selects the external register 20 for only the first cycle period, that is, the one cycle period between the falling time t of the clocks CKI and CKz and t2 (
Figure 2 (C)).

The XR address accesses the external register 20 during one cycle period (1+ to tz) when the external register 20 is selected and reads data (
Figure 2(d)).

The data read from the external register 20 is set in the data register 13 in MPUl0 in the next second half cycle Ctz~t3).

As a result, the external register 20 is released from the MPU10 (FIG. 2(e)). The data transfer process from the external register 20 to the data register 13 is performed in the second half cycle Hz ~
Since it ends at the beginning of the second half cycle (t
Even if the external register 20 is immediately released after entering z~t3) and data can be written and read by accessing from the outside, actual writing and reading are not performed until td in Figure 2.
), there is a time delay, so no problem occurs.

On the other hand, the data in the internal register 11 is stored in the first cycle (
1+~tz), and is read out in the next second half cycle (
The read state is maintained from tg to ts (Fig. 2(f)
)).

In the latter half of the cycle (t's to t3), the calculation means 1
2 performs a predetermined operation on the data read from the internal register 11 and the data read from the data register 13 (FIG. 2(g)). The calculation result is stored in a predetermined location in the internal register 11 in the next cycle (FIG. 2(h)).

Note that the same applies when the processing cycle is two or more cycles.

By doing as described above, the external register 20 is selected only in the first cycle during the processing cycle period in which an operation is performed by the MPU10, and the external register 20 is released in the latter half of the processing cycle. As a result, external registers can be accessed from the outside, and data processing efficiency of the entire system can be improved. Furthermore, since it is possible to freely access the external register 20 from the outside in the latter half of the processing cycle, there is no need to provide a circuit that prohibits access in the second half of the processing cycle, and the entire circuit can be simplified. .

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG. 3 is a block explanatory diagram of the configuration of an embodiment of the present invention, and FIG. 2 is also used as an operation timing chart of the embodiment.

(A) Configuration of Embodiment In FIG. 3, the MPUIO 1 internal register 11, arithmetic means 12, data register 13, and external register 20 are as described in FIG.

In the calculation means 12, 121 is an A-bus multiplexer (A-bus MPX), which inputs one of the input data from the internal register 11, the input data from another calculation unit (not shown), and the input data from the data register 13. Select.

122 is a B bus multiplexer (B bus MPX) that selects one of the input data from the internal register 11 and other arithmetic units.

123 is an arithmetic unit (ALU), and A bus MPXI21
and performs calculations between the data input from the B bus MPX122.

14 is an external register select circuit (X RS EL circuit) which generates an external register select signal (X RS EL double signal). 15 is an external register address register (
The external register address (XR address) for accessing the external register 20 is set in the XRAD register).

21 is an external register multiplexer (XRMPX),
One of the input data from the arithmetic unit 123 of the MPU10 and the input data from external hardware (not shown) is selected and stored in a predetermined location of the external register 20.

(B) Operation of the Embodiment The operation of the embodiment will be explained with reference to the operation timing chart of FIG.

The MPUIO performs predetermined arithmetic processing during two cycles from the falling time t1 of the clock CK to the falling time t3 of the clock CK3 (Fig. 2, mountain)).

On the other hand, the XR3EL circuit 14 generates the XR3EL signal for the first cycle period, that is, the clock CK and C
The external register 20 is selected for one cycle period between the falling time t and tz of K2 (FIG. 2(C)).

The XR address read from the XRAD register 15 accesses the external register 20 during one cycle period (1+~tx>) in which the external register 20 is selected, and reads data (see FIG. 2(d)). ).

The data read from the external register 20 is set in the data register 13 at the beginning of the next second half cycle (tz to t3) (FIG. 2(e)).

As a result, the external register 20 is set to MP in the second half cycle.
Since it is released from U-10, it becomes possible to freely access the external register 20 from external hardware.

On the other hand, the data in the internal register 11 is
+”tz) and is read out in the next second half cycle (t
The read state is maintained from z to ta (Fig. 2(f)
).

In the second half cycle (tz to t3), A bus MPX
121 selects the data in the data register 13, and the B bus MPX 122 selects the data in the internal register 123 and adds it to the ALU 123.

The ALU 123 performs predetermined arithmetic processing in the latter half cycle (tz to t3) (FIG. 2(g)). In the next cycle, the calculation result is stored at a predetermined location in the internal register 11 (FIG. 2(h)).

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(b) External registers are selected only in the first cycle during the arithmetic processing cycle period in which the MPU performs arithmetic operations, and from the next cycle onwards, the external registers are released by the MPU and can be accessed freely from the outside. The amount of waiting for external hardware is reduced, and the data processing efficiency of the entire system can be improved.

(b) Since there is no need for a circuit that prohibits the MPU from accessing the external register from the outside during the entire cycle of arithmetic processing for the data in the external register, the entire circuit can be simplified.

[Brief explanation of the drawing]

Fig. 1: An explanatory diagram of the principle of the present invention. Fig. 2: An operation timing chart of the present invention and an embodiment. Fig. 3: An explanatory diagram of the configuration of an embodiment of the present invention. Fig. 4. . . . Explanatory diagram of a conventional microprocessor data processing control method. FIG. 5 . . . Operation timing chart of a conventional microprocessor data processing control method. 1 and 3, 10... microprocessor (MPU), 11...
・Internal register, 12... Arithmetic means, 13... Data register, 14... External register select (XR3
EL) circuit, 15... External register address (XRA
D) Register, 20...external register.

Claims (1)

[Scope of Claims] A microprocessor (1) that is equipped with an internal register (11) and a calculation means (12), and that performs calculations between data in the internal register (11) and an external register (20) provided outside. 10) In the data processing control method, (
a) A data register (13) is provided inside the microprocessor (10) to which data read from the external register (11) is set; (b) The external register (20 ) and select the external register (20
), the read data is set in the data buffer (13), and (c) in the next cycle, the arithmetic means (12) reads the data between the data buffer (13) and the internal register (11). A data processing control method for a microprocessor, which performs arithmetic processing.