JPS6229813B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence control device that controls the logical sequence of electronic computers, input/output devices, etc. used in information processing systems, and in particular, the present invention relates to a sequence control device that controls the logical sequence of computers, input/output devices, etc. used in information processing systems, and in particular controls the state control and control information output of the control device using a microprocessor. This relates to a sequence control device that is controlled by a program.

Generally, control devices for electronic computers and input/output devices used in information processing systems divide and define internal operations into multiple states depending on their control form, and perform state transitions based on control information generated externally or internally. , it often executes control functions defined for each state and realizes the overall function of a control device. Furthermore, in one defined state, basic small processing units are executed at regular intervals, and the control function in one state is usually achieved by stacking these units. For example, in an input/output control device, if we take as an example the control of a buffer memory that temporarily buffers data between a computer channel (hereinafter simply referred to as a channel) and an input/output device, the input/output control device controls the channel or The state is divided into states such as waiting for a buffer memory access request from an input/output device, reading data from buffer memory in response to a buffer memory access request, or writing data. , can be defined. In addition, in each state, basic small processing units are executed at regular intervals, such as the timing to see an access request, the timing to set a memory address, the timing to perform a memory read, and the timing to perform a memory write. It can be said that the control function is fulfilled.

Conventionally, sequence control devices that perform state control and output control information at fixed time intervals in each state have been assembled using a wired logic control method using general-purpose logic ICs, but the number of states and state transition conditions are limited. If the number of desired control signals is large, the circuit becomes complicated and the amount of hardware (hereinafter abbreviated as H/W amount) becomes too large to fit on one board. Furthermore, in the case of such a wired logic control system, once the logic is solidified, it becomes inflexible.

Nowadays, micro-program control systems have become an effective method in terms of flexibility, and for this reason, highly integrated LSIs such as various sequencers and ROMs have become abundantly available, and the amount of H/W is also decreasing. However, in the conventional microprogram control system, in order to branch to a processing routine corresponding to each state, it is necessary to check each state transition condition one by one using microinstructions. This means that the more state transition conditions there are, the more time it takes for the state transition, and it also means that the bit width of the microinstruction increases due to an increase in the types of microinstructions for condition selection or the number of microinstruction fields. Furthermore, processing routine start addresses corresponding to each state are usually assigned unspecified and programmed, and branch instructions usually have an address field section that specifies the branch destination.

In this way, in conventional micro-program control methods, state transition times are generally slower than in hard-wired logic control methods, and in addition to micro-instructions to obtain desired control information, there are Fields or conditional branch instructions for conditional selection and branch destination specification are required, which complicates programming.Furthermore, an increase in the microinstruction bit width or the variety of microinstructions leads to an increase in the amount of hardware.

The present invention has been made in view of the above points, and is effective mainly in solving the above drawbacks in microprogram control systems.

That is, in the present invention, the address assignment of each microinstruction processing routine corresponding to the control state is as shown in FIG. A microinstruction storage device 1 that stores microinstructions as information, a state address register 2 that selects a microinstruction processing routine corresponding to the control state of the storage device, and a selected storage area (microinstruction processing routine ), an address counter 3 that sequentially reads microinstructions as control information, a control signal generation circuit 4 that decodes the read microinstructions and generates a desired control signal, and a current state address and an external input. A state address generation circuit 5 determines the next control state based on state transition conditions and generates a next state address for selecting a storage area for a microinstruction processing routine corresponding to the next state. - Since the address generation circuit 5 indicates the next state, there is no need to check the state transition conditions with a microinstruction, and one microinstruction sets the next state address in the state address register 2 and sets the address counter 3 to " This is a sequence control device based on a microprogram control system that branches to the start address of a microinstruction processing routine corresponding to the next state by resetting it to 0''.

That is, the embodiment of the present invention can be
The flowchart for branching to the microinstruction processing routine corresponding to the control state under program control is shown in Figure 2.
2, 3, and 4 conditions were required to be determined, but according to the present invention, as shown in the flowchart shown in FIG. 3, only microinstruction 1 is required to branch to the microinstruction processing routine for the next state. be able to. Note that the dotted lines in FIGS. 2 and 3 indicate branches.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a block diagram of an embodiment in which the FIRST IN FIRST OUT (FIFO) function of the buffer memory control section of the input/output control device is controlled using the present invention. The state is defined and the FIFO function is realized.

(1) State “0”: Waiting for a data transfer request from an I/O device or computer channel, and not accessing the buffer memory (2) State “1”: Data transfer from an I/O device to a channel In READ mode, read data from the input/output device is read from the data register of the input/output device interface and written to the buffer memory (3) State “2” In the same READ mode as above , read data from the buffer memory and send the data to the data register of the channel interface (4) State “3” In the WRITE mode where data is transferred from the channel to the input/output device, the buffer - State where write data is read from the memory and sent to the data register of the input/output device interface (5) State “4” In the same WRITE mode as above, the data register of the channel interface The state in which write data is read from the buffer memory and written to the buffer memory.The microinstruction routine that implements the desired control function in the above five states is called as follows, corresponding to the five states. do.

(1) State “0”……IDLE routine (3) State “1”……IOIN routine (3) State “2”……CHOU routine (4) State “3”……IOOUT routine (5) State “4” ”...CHIN Routine The control of the FIFO of the buffer memory of the input/output control device using the present invention is performed using the microinstruction routine defined above, which is assigned addresses and stored as shown in FIG. A storage device 1, a state address register 2 for selecting a storage area for a microinstruction routine corresponding to a control state, an address counter 3 for sequentially reading out microinstructions as control information from the selected storage device, and a readout device. A control signal generation circuit 4 decodes the micro-instructions that have been sent and generates a desired control signal, and a micro-instruction that determines the next control state based on the current state address and state transition conditions from the outside and corresponds to the next state. A state address that generates the next state address to select the routine's storage area.
It consists of an address generation circuit 5, and the block diagram is shown in the fourth section.
As shown in the figure.

The buffer memory section shown here is shown as an example to make the explanation of the present invention easier to understand, and is not intended by the present invention.
WCR, memory read address register
RAR, memory write address register
It consists of WAR, memory address selector SEL, buffer memory BFM, input/output device interface data register IODR, and channel interface data register CHDR. Various control signals are given from the control signal generation circuit, and the buffer - An EMPTY signal 100 indicating that the contents of the word count register WCR are all "0" and a FULL signal 101 indicating that the contents are all "1" are given to the state address generation circuit 5 as memory state signals.

Next, the operation of the present invention will be explained. Now, when a reset signal is given to initialize the buffer memory control, state address register 2, address counter 3, memory read address register RAR, memory write address register WAR, and word・Count register WCR becomes all “0”. When the state address register 2 and address counter 3 become "0", the microinstruction at address 0 of the IDLE routine is read from the microinstruction storage device 1, and after the reset signal is released, this microinstruction is read out from the microinstruction storage device 1.
Execution starts from the microinstruction at address 0 of the IDLE routine. In the embodiment, the microinstruction at IDLE routine address 0 is a state transition instruction, and upon execution of this microinstruction, a state transition signal 102 is output from the control signal generation circuit. State transition signal 102
acts to load the next state address from the state address generation circuit 5 into the state address register 2 and reset the address counter 3 to "0". The state address generation circuit 5 outputs the next state address as shown in FIG. 6 when it is currently in the IDLE routine based on the current state address register 2 and a state transition condition signal from the outside.

Now transfer data from the input/output device to the channel
In the READ mode (given by the mode signal 103 from the interface control unit), the data transfer request IORQ signal 104 from the input/output device and the data transfer request CHRQ signal 10 from the channel
When 5 is “0”, the next state address is the first
As you can see from the figure, the state of the IDLE routine
The address is output, and address 0 of the IDLE routine is given to the microinstruction storage device 1 again. If the state transition condition signal does not change, the microinstruction at address 0 of the IDLE routine will be repeated, and the state transition signal 102 will always be issued. In this state, read data is sent from the input/output device, and when the read data is taken into the input/output device interface data register IODR, the IORQ is sent from the interface control unit 6.
Signal 104 is applied to state address generation circuit 5. As a result, as the output of the state address generation circuit 5, since the FULL signal 101 is "0" in the initial state, the state address "1" is output, and the state address register is set in the next microinstruction execution cycle. 2 is set to "1", address counter 3 becomes "0", and address [10] ₈ is given to microinstruction storage device 1. Address [10] ₈ is
This is the start address of the IOIN routine, and from the next microinstruction execution cycle, the 0 of the IOIN routine
The microinstruction from the address is executed.

The IOIN routine starts execution from microinstruction 10 as shown in the flowchart of FIG. is applied to address input A of buffer memory BFM. Since microinstruction 10 is not a state transition instruction, state address register 2 does not change and the address counter is incremented by 1 by the clock signal, so that in the next microinstruction execution cycle, address [11] ₈ will be provided to the microinstruction memory 1. Address [11] ₈ is address 1 of the IOIN routine, where microinstruction 11 is executed. Microinstruction 11 is
I/O device interface data register
Transfer the contents of IODR to the data bus DBUS
IODR out enable signal 107 and data on data bus DBUS to buffer memory
A memory write strobe signal 108 is provided for writing to the BFM, respectively. microinstruction 1
After execution of microinstruction 1, only the address counter is incremented by 1 as in the case of execution of microinstruction 10, and in the next execution cycle, microinstruction 12 will be executed.
Microinstruction 12 indicates that signal 109 which increases memory write address register WAR by 1 is WAR.
The following microinstruction 13 is given to the word
Signal 110 to add 1 to count register WCR
to the WCR, and the microinstruction 14 provides the interface control unit 6 with a signal 111 for resetting the data transfer request signal IORQ.

As described above, when microinstructions 10 to 14 are sequentially executed and the execution cycle of microinstruction 15 is entered, since microinstruction 15 is a state transition instruction, state transition signal 102 is issued. At this time, the state address generation circuit 5 outputs the next state address shown in FIG.・Address register 2 is loaded with “0” or “2”,
Address counter 3 is reset to "0". That is, by executing the microinstruction 15,
Address [00] ₈ or [20] ₈ is applied to microinstruction store 1, resulting in a branch to the starting address of the IDLE or CHOUT routine.

If it branches to the IDLE routine, it is as described above, and if it branches to the CHOUT routine, the fifth
Execution begins with microinstruction 20 shown in the flowchart of the figure. Microinstruction 20 provides the contents of memory read address register RAR to address input A of buffer memory BFM via memory address select signal 106. The microinstruction 21 sends the buffer memory BFM data to the memory data out enable signal 11.
2 onto the data bus DBUS and into the channel interface data register CHDR.
Write signal 113 writes data on data bus DBUS. Microinstruction 22 increments the contents of memory read address register RAR by one by RAR count up signal 114. Microinstruction 23 is word count register
WCR countdown signal 115
-1. The microinstruction 24 provides the interface control unit 6 with a signal 116 that resets the data transfer request CHRQ signal. microinstruction 25
is a state transition instruction, and the state address generation circuit 5 outputs the next state address shown in FIG. 8, and after the microinstruction 25 is executed,
Branch to IDLE routine or IOIN routine.

IDLE, IOIN, in READ mode
Branch to CHOUT routine from external CHRQ,
Determined by IORQ, EMPTY, FULL signals,
The buffer memory is used to sequentially retrieve the read data stored in memory in the IOIN routine and transfer it to the channel in the CHOUT routine.
I have explained FIFO control, but WRIT
For FIFO control in IDLE mode,
The IOOUT and CHIN routines are executed in the same sequence.

As described above, in the sequence control device using the microinstruction control method of the present invention, each microinstruction processing routine corresponding to the control state is allocated to each divided storage area, and the address for selecting the storage area is assigned to the state address generation circuit. The start address of each microinstruction processing routine is determined from external state transition conditions and the current state address, and is fixed at address 0 in the divided storage area, allowing one microinstruction to handle the next control state. can branch to a microinstruction processing routine that

Here, if the embodiment is carried out in the conventional manner, the flow from the IDLE routine in the READ mode to the IOIN routine will be as shown in FIG. In other words, the mode from the outside that is the branch condition,
The CHRQ, IORQ, EMPTY, and FULL signals are examined by microinstructions and branched to each processing routine.The conditions for branching to the IOIN routine are that the mode signal is READ mode, the IORQ signal is "1", and FULL is selected. It is a necessary condition that the signal is "0", and for this purpose, it is necessary to execute the condition judgment instructions of microinstructions 1, 2, and 3, and further, to branch to the IOIN routine, it is necessary to execute microinstruction 4. do. Furthermore, if the IORQ signal becomes "1" after microinstruction 3, the branch to the IOIN routine will be further delayed by the execution time of microinstructions 5 and 6.

As described above, the sequence control device using the microinstruction control method according to the present invention has improved processing speed compared to the conventional device which uses microinstructions to check state transition conditions. In addition, since there is no need to judge conditions or specify branch destinations using microinstructions, H/
The amount of W can also be reduced compared to the conventional method.

The embodiment described above is only an example.

The example describes buffer memory FIFO control, but it also applies to computer arithmetic control, channel control, etc.
It may be interface control or input/output device interface control.

Further, in the embodiment, there is one state address register and one state address generation circuit, but in order to further control the higher level state or the lower level state, the first state address register and the state address generation circuit are provided. Two or more types of state address registers and state address generation circuits may be provided, such as a first state address generation circuit, a second state address register, and a second state address generation circuit.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, in which microinstruction processing routines corresponding to each control state are allocated to address areas corresponding to the contents of a state address register 2 on a microinstruction storage device 1.
FIG. 2 is a flowchart of microinstruction execution when the embodiment branches to a microinstruction processing routine corresponding to a control state using the conventional method, and FIG. FIG. 4 is a flowchart of microinstruction execution when the microinstruction storage device 1, state address register 2, address counter 3, control signal generation circuit 4,
FIG. 5 is a block diagram when the present invention comprising a state address generation circuit 5 is implemented in a buffer memory FIFO control device of an input/output control device.
FIG. 6 is a flowchart when executing the microinstruction sequence of the CHOUT routine. In this embodiment, when the current state address is "0" (IDLE routine), the state transition condition signals 100, 101, 10
FIG. 7 is a diagram showing the next state address output by the state address generation circuit 5 by 3, 104, and 105. In the embodiment, when the current state address is "1" (IOIN routine), the state Transition condition signals 100, 101, 103, 104,
105 shows the next state address output by the state address generation circuit 5, No. 8
The figure shows an example and the current state address is “2”
(CHOUT routine) is a diagram showing the next state address output by the state address generation circuit 5 according to the state transition condition signals 100, 101, 103, and 105. In the drawings, the same or corresponding parts are denoted by the same reference numerals. In the figure, 1 is a microinstruction storage device, 2 is a state address register,
3 is an address counter, 4 is a control signal generation circuit, 5 is a state address generation circuit, and 6 is an interface control section.

Claims (1)

[Claims] 1 Multiple control states are defined within the control device,
A microinstruction storage device that stores microinstructions, which are control information for performing desired control in each control state, in a storage area corresponding to each control state; A state address register that selects a storage area for an instruction processing routine, an address counter that sequentially reads microinstructions that are control information from the selected storage area, and a state address register that decodes the read microinstructions and executes them as desired. The control signal generation circuit that generates control signals and the current state
A state address generation circuit that determines the next control state based on the address and external state transition conditions, and generates the next state address for selecting the storage area where the corresponding microinstruction processing routine is stored. and the state address generation circuit indicates the next state, so that one
A programmable sequence control device characterized in that a microinstruction branches to a start address of a microinstruction processing routine corresponding to a next control state.