JPH0820941B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a data processing control system of an MPU when performing arithmetic between data in a register inside a microprocessor (MPU) and data in an external register, a data register is provided in the MPU,
Select the external register only in the first one cycle of the operation processing cycle, set the data in the data register, release the external register from the MPU to enable external access, and then read the data in the data register in the next cycle. And calculate. As a result, the data processing efficiency of the entire system can be improved and the circuit configuration can be simplified.

[Industrial applications]

The present invention relates to a data processing control method for a microprocessor, and more particularly to a data processing control method for performing an operation between data in a register outside the microprocessor and data in a register inside the microprocessor.

[Conventional technology]

In the microprocessor, in addition to the arithmetic processing between the respective data in the internal registers, the arithmetic between the data in the registers outside the microprocessor and the data in the internal registers of the microprocessor is performed.

FIG. 4 is a block diagram showing a data processing control system of a conventional microprocessor for data of an external register.

In FIG. 4, 30 is a one-chip type microprocessor (MPU), and 40 is an external register.

In the MPU 30, 31 is a general-purpose internal register that stores the data to be operated and the operation result. An A bus multiplexer (A bus MPX) 32 selects one of input data from the internal register 31, input data from another arithmetic unit (not shown) and input data from the external register 40. A B-bus multiplexer (B-bus MPX) 33 selects one of the input data from the internal register 31 and another arithmetic unit. 34 is an arithmetic unit (ALU), which is an A bus MPX32 and a B bus
Performs calculations on the data input from the MPX33. 35 is an external register select circuit (XRSEL circuit), which is an external register 4
An external register select signal (XRSEL signal) that selects 0 is generated. An external register address register (XRAD register) 36 is set with an external register address (XR address) for accessing the external register 40.

41 is an external register multiplexer (XRMPX), MPU30
One of the input data from the arithmetic unit 34 and the input data from external hardware (not shown) is selected and stored in a predetermined location of the external register 40.

Next, the operation of FIG. 4 will be described with reference to the operation timing chart of FIG.

In FIG. 5, CK ₁ , CK _{2 and the} like are clocks for MPU control, and one cycle is formed between the clocks CK ₁ and CK _2, between CK ₂ and CK _3, etc. (FIG. 5A).

Between 2 cycles from the falling time t ₁ of the clock CK ₁ to the fall time t ₃ of the clock CK _3, processing is performed in the MPU 30 (FIG. 5 (b)). Along with that, XRSEL circuit 3
5 generates the XRSEL signal and selects the external register 41 during the two-cycle period of t ₁ to t ₃ (FIG. 5 (c)). XRSE
During the two cycle periods of t ₁ to t ₃ selected by the L signal, the external register 41 cannot be accessed except for the MPU 30.

Internal register 31 at the falling edge t ₁ of clock CK ₁
When accessed, the read data is B bus MP
It is sent to X33 (Fig. 5 (e)).

On the other hand, at the falling time point t ₁ of the clock CK ₁ , the XRSEL signal is generated, the address is read from the XRAD register 36, and the external register 40 is accessed. Since there are many MPUs (not shown) other than the MPU 30, the data reading from the external register 40 is performed by sending the data rather than the reading from the internal register (FIG. 5 (d)).

In the second half of the cycle (t ₂ ~t _3), A bus MPX32 selects the data of the external register 40, B Bus MPX33 is added to ALU34 by selecting data in the internal register 31.

When the ALU34 completes a predetermined operation (FIG. 5 (f)), the operation result is stored in a predetermined location of the external register 40 via the internal register 31 or XRMPX41 in the next cycle (FIG. 5 (g). )).

By repeating the above processing, the calculation is performed in units of two cycles.

[Problems to be solved by the invention]

The conventional microprocessor data processing control method is
As described above, the operation is performed in units of two cycles, and the external register 40 is selected by the MPU 30 during this period. Then, during the 2-cycle period selected by the MPU30, the external hardware such as the peripheral device has an external register.
You can't access 31 and have to wait.

Therefore, there is a problem in that the data processing efficiency of the entire system including external peripheral devices is reduced.

If the external register 40 is externally accessed and data is written during the latter half cycle (t _{2 to} t ₃ ) in which the MPU 30 is performing arithmetic processing, the contents of the read data of the MPU 30 will change. There is a fear. Therefore, there is a problem that a special hardware circuit for prohibiting access from the outside must be provided during the latter half cycle period as well as the first half cycle.

According to the present invention, the operation is performed by the MPU 30 and the external register 40 is cycled only for the first one cycle in the processing cycle period, and the external register 40 is cycled in the subsequent processing cycles.
By releasing more and making it accessible from the outside,
It is an object of the present invention to improve the data processing efficiency of the entire system and to provide a data processing control system of a microprocessor which does not require a special circuit for prohibiting external data writing to the external register 40.

[Means for solving problems]

The solution taken by the present invention will be described with reference to FIG. FIG. 1 is a diagram for explaining the principle of the present invention.

In FIG. 1, 10 is a microprocessor (MPU), and 20 is an external register.

In the MPU10, 11 is an internal register, which stores operation data. Reference numeral 12 denotes an arithmetic means, which performs arithmetic processing on input data.

The XRSEL signal is a signal for selecting the external register 20 and is supplied from the MPU 10 or the outside of the MPU 10. The XR address is the address to access the external register 20, and the MPU10
Or supplied from outside the MPU10.

Reference numeral 13 is a data register to which the data read from the external register 20 is set. The data read from the data register 13 is supplied to the arithmetic means 12. Note that this data register may use an existing register in the MPU 10 as a data register.

[Work]

The operation of FIG. 1 will be described with reference to the operation timing chart of FIG.

In FIG. 2, CK ₁ , CK _2, etc. are clocks for MPU control, and one cycle is formed between adjacent clocks (second
Figure (a)).

MPU10, the clock CK from the falling point in time t ₁ of the clock CK ₁
Between ₃ 2 cycles to falling time t _3, performs predetermined calculation processing (FIG. 2 (b)). The two cycles may be two cycles between the rising points of the clocks CK ₁ and CK ₃ .

On the other hand, the XRSEL signal selects the external register 20 for the first first cycle period, that is, for one cycle period between the falling times t ₁ and t _{2 of the} clocks CK ₁ and CK ₂ (FIG. 2 (c)).

XR address, external register 20 in 1 cycle period which the external register 20 is a select (t ₁ ~t ₂₎
Is accessed to read data (FIG. 2 (d)).

Data read from the external register 20, in the next second half of the second cycle (t ₂ ~t _3), is set in the data register 13 in the MPU 10. This allows external registers
20 is released from the MPU 10 (Fig. 2 (e)). The data transfer process from the external register 20 to the data register 13
Since ends in the first second half of the second cycle (t ₂ ~t _3), immediately to the external register 20 to the released state when the second half of the second cycle (t ₂ ~t _3), data is accessed from the outside Even if the writing and reading are possible, there is no problem because the actual writing and reading have a time delay as shown in FIG. 2 (d).

On the other hand, data in the internal register 11 is read in the initial first cycle (t ₁ ~t _2), read state is maintained until the next second half cycle (t ₂ ~t ₃₎ (FIG. 2 (f )).

In the second cycle (t _{2 to} t ₃ ) of the latter half, the calculation means 12
Performs a predetermined operation on the data read from the internal register 11 and the data read from the data register 13 (FIG. 2 (g)). The calculation result is stored in a predetermined location of the internal register 11 in the next cycle (FIG. 2 (h)).

The same applies when the processing cycle is two cycles or more.

By doing so, the external register 20 is selected only for the first one cycle in the processing cycle period in which the MPU 10 operates, and the external register 20 is released in the latter half processing cycle. As a result, the external register can be accessed from the outside, and the data processing efficiency of the entire system can be improved. Further, since it is possible to freely access the external register 20 from the outside in the latter half of the processing cycle, it is not necessary to provide a circuit for prohibiting access in the latter half of the processing cycle, and the entire circuit can be simplified. .

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG. 3 is a block diagram of the configuration of an embodiment of the present invention, and FIG. 2 is also used as an operation timing chart of the embodiment.

(A) Configuration of Embodiment In FIG. 3, MPU 10, internal register 11, arithmetic means 1
2. The data register 13 and the external register 20 are as described in FIG.

In the arithmetic means 12, 121 is an A bus multiplexer (A bus MPX), which receives input data from the internal register 11,
One of the input data from the other arithmetic unit (not shown) and the input data from the data register 13 is selected. 122 is a B bus multiplexer (B bus MPX), which is an internal register 1
1 or one of the input data from the other arithmetic units is selected.

Reference numeral 123 is an arithmetic unit (ALU), which is an A bus MPX121 and a B bus MPX1.
Operates on the data input from 22.

An external register select circuit (XRSEL circuit) 14 generates an external register select signal (XRSEL signal). Fifteen
Is an external register address register (XRAD register),
The external register address (XR address) for accessing the external register 20 is set.

21 is an external register multiplexer (XRMPX), MPU10
One of the input data from the arithmetic unit 123 and the input data from external heart wear (not shown) is selected and stored in a predetermined location of the external register 20.

(B) Operation of the Embodiment The operation of the embodiment will be described with reference to the operation timing chart of FIG.

MPU10, the clock CK from the falling point in time t ₁ of the clock CK ₁
Between ₃ 2 cycles to falling time t _3, performs predetermined calculation processing (FIG. 2 (b)).

On the other hand, the XRSEL circuit 14 generates the XRSEL signal, and the first one cycle period, that is, the falling point of the clocks CK ₁ and CK _2.
The external register 20 is selected only for one cycle period between t ₁ and t ₂ (FIG. 2 (c)).

The XR address read from the XRAD register 15 accesses the external register 20 during one cycle period (t _{1 to} t ₂ ) in which the external register 20 is selected to read data (see FIG. 2 ( d)).

Data read from the external register 20, the beginning of the next second half cycle (t ₂ ~t _3), the data register 13
(FIG. 2 (e)). As a result, since the external register 20 is released from the MPU 10 in the latter half cycle, the external register 20 can be freely accessed by external hardware.

On the other hand, data in the internal register 11 is read in the first cycle (t ₁ ~t _2), the next second half cycle (t ₂
Read state is maintained until ~t ₃₎ (FIG. 2 (f)).

In the latter half cycle (t _{2 to} t ₃ ), the A bus MPX121 selects the data of the data register 13 and the B bus MPX122 selects the data of the internal register 123 and adds it to the ALU 123.

ALU123, in the second half of the cycle (t ₂ ~t ₃₎ performing a predetermined arithmetic processing (FIG. 2 (g) in. The next cycle, the operation result is stored in a predetermined location of the internal register 11 (the Figure 2 (h)).

〔The invention's effect〕

As described above, according to the present invention, the following effects can be obtained.

(B) Since the external register is selected only in the first one cycle in the arithmetic processing cycle period in which the operation is performed by the MPU, and after the next cycle, the external register is released from the MPU and can be freely accessed from the outside. It is possible to improve the data processing efficiency of the entire system by reducing the waiting time of external hardware.

(B) Since the MPU does not need a circuit for prohibiting external access to the external register during the entire cycle of the arithmetic processing for the data in the external register, the entire circuit can be simplified.

[Brief description of drawings]

FIG. 1 ... Principle explanatory diagram of the present invention, FIG. 2 ... Operation timing chart of the present invention and the embodiment, FIG. 3 ... Configuration explanatory diagram of one embodiment of the present invention, FIG. Of the data processing control method of the microprocessor of FIG. 5, FIG. 5 ... Operation timing chart of the data processing control method of the conventional microprocessor. 1 and 3, 10 ... Microprocessor (MPU), 11 ... Internal register, 12 ... Arithmetic means, 13 ... Data register, 14 ... External register select (XRSEL) circuit, 15 ... External register address (XRAD) register, 20 ... External register.

Claims (1)

[Claims] 1. An internal register (11) and an arithmetic means (12) are provided inside, an external register (20) provided outside is selected in a first cycle, and an internal register (11) is selected in a second cycle. In a microprocessor (10) for performing an operation between data in an external register (20), (a) a data register (13) in which data read from the external register (20) is set; Means for selecting the external register (20) only for one cycle, reading the data of the external register (20) and setting it in the data register (13), and (c) a data register by the operation means (12) in the second cycle. (13) A means for performing arithmetic processing between data in an internal register (11) and a microprocessor.