JPH0677232B2 - Micro program controller - Google Patents

Description

The present invention relates to a micro program control device, and more particularly to a micro program control device suitable for use in image processing and the like.

[Conventional technology]

In image processing using a micro program control device, since the amount of data to be processed is enormous, reducing the number of steps even with one micro program step leads to improvement in processing speed.

For example, in the case of processing image data of 1000 × 1000 pixels, assuming that one microprogram step is executed at a speed of 200 ns, it takes 0.2 seconds per microprogram step to process all data. It will take time. Therefore, if 10 microprogram steps are required for the entire microprogram, the total time required for the microprogram is 2 seconds. Therefore, it is an important issue to reduce the number of steps of the microprogram.

However, in the conventional micro program control device of this type, the operation designated by the operation field of the micro instruction is processed by the arithmetic unit to execute the micro instruction. Therefore, the micro instruction is executed by one micro instruction. The number of operations was limited to one, and there was a limit to reducing the number of steps of the microprogram.

[Problems to be solved by the invention]

The conventional microprogram control device described above can execute only one operation with one microinstruction, so that it is difficult to reduce the number of steps of the microprogram.

In view of the above points, an object of the present invention is to provide a microprogram control device capable of reducing the number of steps of a microprogram by enabling different operations to be simultaneously executed by one microinstruction. is there.

[Means for solving problems]

A microprogram control device of the present invention includes a microprogram memory for storing a microprogram composed of a plurality of microinstructions, an address sequencer for generating a microprogram address and giving it to the microprogram memory, and the microprogram in the microprogram memory. A pipeline register that stores a microinstruction read from an address in association with at least an operation field, an address field, and a register field, an arithmetic unit that operates according to an operation specified by the operation field of the microinstruction, and this arithmetic unit Random access memory and registers connected to the source bus, reference bus, and destination bus of the One that performs a load operation, a count-up operation, a count-down operation, a count-up operation, and a count-down operation according to the load instruction, count-up instruction, and count-down instruction specified in the register field of the microinstruction, connected to the master, reference, and destination buses. It has the above counter.

[Action]

In the micro program control device of the present invention, the micro program memory stores a micro program composed of a plurality of micro instructions, the address sequencer generates a micro program address and supplies the micro program address to the micro program memory, and the pipeline register is a micro program memory. The microinstruction read from the program address is stored in correspondence with at least the operation field, the address field and the register field, the arithmetic unit operates according to the operation specified in the operation field of the microinstruction, and the random access memory and the register group are stored. One or more counters connected to the source bus, reference bus, and destination bus of the arithmetic unit Nsubasu and destination is connected to the bus microinstruction been loaded instruction specified by the register field of the load operation in accordance with the count-up instruction and counting down instruction, the count-up operation and a count-down operation performed.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a microprogram controller according to an embodiment of the present invention. The microprogram control device of this embodiment includes a microprogram memory 1, a pipeline register 2, an address sequencer 3, a mapping array 4, a multiplexer 5 for selecting a branch condition, a multiplexer 6 for selecting a branch address,
Arithmetic unit 7, address buffer 8, random access memory (hereinafter abbreviated as RAM) 9, register group 10, M counter 11 and N counter 12, and latch 13
A programmable logic array (hereinafter abbreviated as RLA) 14 and an image memory 15 constitute a main part thereof.

The micro program memory 1 is a memory that stores a micro program including a plurality of micro instructions. For example, a microprogram as shown in FIG. 4 is stored as one of the microprograms.

The pipeline register 2 is connected to the output side of the microprogram memory 1 and has a sequence clock SE.
The microinstruction 20 (see FIG. 2) of the microprogram address generated by the address sequencer 3 according to (see FIG. 3 (a)) is read from the microprogram memory 1 and the operation field 21 and address of the microinstruction 20 are read. Field 22 and counter field 2
It is designed to store in correspondence with 3. The output of the pipeline register 2 is connected to the multiplexer 5 and the arithmetic unit 7 for selecting the branch condition by the operation bus 2a corresponding to the operation field 21, and the multiplexer 6 for selecting the branch address by the address bus 2b corresponding to the address field 22. And the operand bus 2c corresponding to the register field 23 is connected to the PLA 14.

The address sequencer 3 counts up the start address of the microprogram supplied from the mapping array 4 according to the sequence clock SE to generate a microprogram address, and supplies the generated microprogram address to the microprogram memory 1. The address sequencer 3 also selects the branch address from the multiplexer 6 that selects the branch address according to the output of the multiplexer 5 that selects the branch condition.

The mapping array 4 generates the start address of the corresponding microprogram from the given microinstruction and supplies it to the address sequencer 3.

The arithmetic unit 7 is a unit that operates according to the operation designated by the operation field 21 of the microinstruction 20 stored in the pipeline register 2. In the arithmetic unit 7, the source terminal S is the source bus 7a.
The reference terminal R is connected to the reference bus 7b, and the destination terminal D is connected to the destination bus 7c. In addition, the operation terminal has a pipeline register 2 via the operation bus 2a.
The status terminals are connected to the latch 13.

The address buffer 8 is a buffer that stores an address or a value output from the multiplexer 6 that selects a branch address, and its output is connected to the source bus 7a and the reference bus 7b of the arithmetic unit 7.

The RAM 9 is connected to the source bus 7a, the reference bus 7b and the destination bus 7c of the arithmetic unit 7 and has a write enable clock WE (see FIG. 3 (a)).
Depending on the calculation unit 7, M counter 11 or N counter 1
The output from 2 is written and the data is read to the source bus 7a or the reference bus 7b.

The register group 10 is connected to the source bus 7a, the reference bus 7b and the destination bus 7c of the arithmetic unit 7 and also to the image memory 15,
The output of the arithmetic unit 7 or the data of the image memory 15 is input / output according to the write enable clock WE.

Although the M counter 11 and the N counter 12 are composed of ordinary counters, as will be described later in detail, the micro instruction 20
If either or both of M and N are designated in the register field 23 of the above, a load operation, a count-up operation or a count-down operation will be executed, so that they are called M counter and N counter for convenience.
These M counter 11 and N counter 12 are connected to the source bus 7a, the reference bus 7b and the destination bus 7c of the arithmetic unit 7 and
Of the M counter 11 and the N counter 12 or both of them can be loaded based on the load signal, count up signal or count down signal from the PLA 14
It is designed to count up or count down. In addition, M counter 11 and N counter 12
Is connected to the multiplexer 6 for selecting the branch address and the RAM 9.

The latch 13 is connected to the status terminal of the arithmetic unit 7 and latches the status of the arithmetic unit 7 according to the write enable clock WE. The output of this latch 13 is connected to a multiplexer 5 which selects a branch condition.

The PLA 14 is connected to the operand path 2c corresponding to the register field 2c of the pipeline register 2 and writes one or both of the M counter 11 and the N counter 12 specified by the register field 23 of the microinstruction 20. The load operation is performed according to the enable clock WE, and the count up operation or the count down operation is performed according to the count clock CNT (see FIG. 3B).

The image memory 15 is a memory for inputting and outputting image data via the register group 10.

Referring to FIG. 2, the microinstruction 20 used in the microprogram controller of the present embodiment comprises an operation field 21, an address field 22 and a register field 23. In the operation field 21, an operation such as a function or branch of the arithmetic unit 7 is specified, and the address field 22
In the register field 23, the RAM 9 connected to the source bus 7a, the reference bus 7b and the destination bus 7c, the register group 10, the M counter 11 and the N counter 12 are designated.

By the way, a characteristic of the microinstruction 20 used in the microprogram control device of the present embodiment is that M or N is specified not only in the address field 22 but also in the register field 23, or both are specified.
Either or both of the counter 11 and the N counter 12 can be designated, and further, the register field
By specifying 23 as M +, N +, M-, N-, MN +, MN-, NM + or NM-, it is possible to specify the count-up operation or count-down operation of either or both of M counter 11 and N counter 12 at the same time. That's what it looks like.

Specifically, by designating as M +, N +, M- or N-, the designated M counter 11 or N counter 12 can count up or down the count value and output it to the source bus 7a or the reference bus 7b. it can. Also, by designating as MN +, MN-, NM + or NM-, the M counter 11 and the N counter 12 simultaneously count up or count down, and the count value of the counter designated first is sourced. It can be output to the bus 7a or the reference bus 7b.

Further, in the microprogram control device of the present embodiment, as shown in, for example, FIGS.
It is set to 0 ns, and the first 60 ns in one cycle is the sequence clock SE, and 120 to 180 ns in one cycle is the write enable clock WE. Also, the count clock CNT is the latter half 20ns of the sequence clock SE.
Is set to correspond to.

Next, the operation of the microprogram controller of the present embodiment having such a configuration will be described.

Note that the microprogram shown in FIG. 4 will be described here as an example.

When a microinstruction designating a microprogram is input, the mapping array 4 outputs the start address of the microprogram corresponding to the microinstruction.

The address sequencer 3 which receives the start address of the microprogram from the mapping array 4 gives this start address to the microprogram memory 1 in synchronization with the sequence clock SE. At the same time, the micro instruction (CLRN) of the first step of the micro program stored at the start address is read from the micro program memory 1 synchronized with the sequence clock SE to the pipeline register 2.

Next, the arithmetic unit 7 uses the micro instruction of the first step.
Performs the operation specified in the operation field 21 of 20. As a result, the N counter 12 is cleared to zero.

When the execution of the first step of the microprogram is completed, the address sequencer 3 counts up according to the sequence clock SE, and the address given to the microprogram memory 1 is incremented. As a result, the micro-instructions 20 after the second step are sequentially executed. Third step microinstruction (MEMR
D) and the fourth step microinstruction (MOVE MEMREG,
In RAM-M), the data in the image memory 15 is stored in the register group 10
It is transferred to address 21 of RAM9 via the register inside.

When the fifth step microinstruction (COMP NM +, $ 4) is read to the pipeline register 2, the M counter 11 and the N counter 12 are respectively incremented by +1 according to the count clock CNT according to the designation (NM +) in the register field 23.
Only, and the count-up output (value "1") of the N counter 12 is output to the reference bus 7b. Further, the value "4" is stored in the address buffer 8 according to the designation in the address field 22, and this value "4" is output to the source bus 7a.

Therefore, the arithmetic unit 7 executes the comparison (COMP) specified in the operation field 21 of the microinstruction 20 with respect to the value "4" of the source bus 7a and the value "1" of the reference bus 7b.

At the first passage of the micro-instruction 20 in the fifth step, the value “4” at the source terminal S of the arithmetic unit 7 is smaller than the value “1” at the reference terminal R, and the difference becomes negative. A status to that effect is output, and this status is latched in the latch 13 in response to the write enable clock WE.

Therefore, the next 6th step microinstruction (JLT * A
The branch address (* AA) is selected by the multiplexer 5 which selects the branch condition at the time of execution of A), and the control returns to the third step. As a result, similar processing is repeated.

When the microinstructions 20 in the third to sixth steps are repeatedly executed in this way, the microinstructions 20 in the fifth step are executed.
In the fourth loop of, the count-up output of the N counter 12 output to the reference bus 7b becomes the value "4", and the latch 13 does not latch the status indicating that the difference is negative. As a result, the multiplexer 5 that selects the branch condition does not operate when the micro instruction 20 of the sixth step is executed,
The control is not returned to the microinstruction 20 in the third step, the process moves to the microinstruction (NEXT) in the seventh step, and the processing of the microprogram designated by the microinstruction is ended.

Thus, in the microprogram controller of the present embodiment, loading, counting up or counting down of the M counter 11 and the N counter 12 and other operations,
For example, comparison can be performed in one microprogram step. Therefore, the microprogram using the microinstruction by the microprogram controller of the present embodiment shown in FIG. 4 performs the same processing as the microprogram by the conventional microprogram controller shown in FIG. Compared to the program, the two steps surrounded by the solid line in FIG. 5 can be shortened, and the execution time of the microprogram can be shortened accordingly.

〔The invention's effect〕

As described above, according to the present invention, the instruction for loading, counting up, and counting down the counter can be performed not only in the field for designating the operation of the microinstruction but also in the field for designating the register. , Count-up (increment) or count-down (decrement) and other operations such as comparison can be executed in one microprogram step, and the number of microprogram steps can be shortened to improve the processing speed of image data and the like. The effect is that it can be achieved.

Further, by enabling a plurality of counters to be loaded, counted up, or counted down at the same time, the number of steps of the microprogram can be further shortened, and the processing speed of image data and the like can be further improved. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of microinstructions used in the microprogram controller of the present embodiment, and FIGS. 3 (a) and 3 (b). Are timing charts showing various clocks in the micro program controller of the present embodiment, FIG. 4 is a diagram showing an example of a micro program executed by the micro program controller of the present embodiment, and FIG. 5 is shown in FIG. It is a figure which shows an example of the conventional microprogram which performs the completely same process as the shown microprogram. In the figure, 1 ... Microprogram memory, 2 ... Pipeline register, 3 ... Address sequencer, 4 ... Mapping array, 5 ... Multiplexer for selecting branch condition, 6 ... Multiplexer for selecting branch address, 7 ...... Arithmetic unit, 7a Source bus, 7b Reference bus, 7c Destination bus, 8 Address buffer, 9 Random access memory, 10 Registers, 11 M counter, 12 ... N counter, 13 latch, 14 programmable logic array, 15 image memory, 20 micro instruction, 21 operation field, 22 address field, 23 register field.

Claims (1)

[Claims] 1. A microprogram memory for storing a microprogram composed of a plurality of microinstructions, an address sequencer for generating a microprogram address and giving it to the microprogram memory, and reading from the microprogram address of the microprogram memory. A pipeline register that stores the generated microinstruction in association with at least an operation field, an address field, and a register field, an arithmetic unit that operates according to the operation specified in the operation field of the microinstruction, and a source bus of this arithmetic unit, Random access memory and register group connected to the reference bus and destination bus, and the source bus and reference bus And one or more counters connected to the destination bus and performing a load operation, a count-up operation and a count-down operation in accordance with a load instruction, a count-up instruction and a count-down instruction designated by a register field of the microinstruction. Micro program control device.