JPH0575985B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention involves inputting a logic test pattern into a digital circuit such as an integrated circuit (IC, LSI), memory, microcomputer, etc., and testing the resultant logic output to match an expected value pattern. Related to pattern readout test equipment that can efficiently read and generate a large number of test patterns in test equipment (e.g., logic testers, memory testers) that performs comparison tests to determine whether the circuit under test is good or bad. It is.

[Prior art]

Generally, in this type of test equipment, tests are performed by repeatedly inputting the test pattern stored in the pattern memory into the circuit under test, but in order to make effective use of the pattern memory, the test pattern is , order information defining the reading order is stored in the pattern memory, and the address of the pattern memory to be read next is generated in accordance with the order information.

The prior art will be further explained below with reference to the drawings.

FIG. 1 is a system configuration diagram of an example of a conventional test pattern readout control system.

First, if the value of the address counter indicates address #0, the test pattern "01010100" stored at address #0 of the pattern memory is read out and applied to the circuit under test.

On the other hand, the control section reads out the test pattern, reads out and decodes the corresponding order information, and gives the address counter the relevant operation instruction.

FIG. 2 is a correspondence diagram of order information and operation contents.

According to this, since address #0 in FIG. 1 has order information "NOP", the control section simply instructs the address counter by +1.

As a result, in the next cycle, the address counter points to address #1, and the test pattern "00010100" stored there as well as the sequence information "LOOP 3 times" are read out.

This order information "LOOP 3 times" means that the section of the order information until the order information "LOOPEND" is read out is repeated up to three times.

Furthermore, the control unit adds +1 to the address counter.
When the instruction is given, the address will be updated to address #2 in the next cycle, and the order information "SUB #6 address" will be updated.
According to this, the program branches to address #6.

Since address #6 has the order information "NOP", the address is advanced to address #7 in the next cycle.

At address #7, according to the order information "RET", in the next cycle it returns to address #3, and in response to the order information "LOOPEND", it returns again to the start address #1 of the loop.

Thereafter, the addresses are sequentially updated in the same manner according to the order information, and the test patterns stored there are read out.

However, in recent years, as circuits under test have become faster and more complex, there has been a strict requirement to generate a large number of test patterns at high speed.

However, in the above-mentioned conventional method, reading and decoding of sequential information, address instruction according to the result, address update, etc. must be performed within one cycle, and in order to increase operation speed, the memory speed of sequential information must be extremely high. It is necessary to make it higher.

Furthermore, since there is a one-to-one correspondence between sequence information and test patterns in the pattern memory, storing a large number of test patterns requires a sequence information memory capacity with a correspondingly large depth.

Therefore, the conventional method described above not only requires the use of a large amount of expensive high-speed memory, which increases the cost of the device. Since it is necessary to implement this, the problem of signal delay due to the wiring must also be solved. In this way, in the conventional method, increasing the number of test patterns and increasing the speed of pattern generation are contradictory conditions.
It was difficult to achieve these simultaneously.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an economical pattern reading test device that eliminates the drawbacks of the prior art described above and can efficiently read and generate a large number of test patterns at high speed.

[Summary of the invention]

The configuration of the pattern readout test device according to the present invention is such that various test patterns, readout order information, and expected value patterns corresponding to each test pattern are stored, and the test pattern is read out according to the order information. In a test device that has a function of reading and inputting the above-mentioned circuit into the circuit under test and comparing the output of the circuit under test with the expected value pattern corresponding to the test pattern to determine the quality of the circuit under test, each of the above-mentioned A first storage means that stores a test pattern in advance, a first addressing means that generates and specifies a read address of the first storage means, control contents for the first addressing means, and the following: a second storage means for storing a program instruction including an instruction regarding a storage location of an instruction to be executed; a second addressing means for specifying a read address of the program instruction with respect to the second storage means; When the instruction read from the second storage means corresponds to a no-operation, the address specified by the first addressing means is
fixing the address specified by the second addressing means until it matches the address value indicated by the instruction corresponding to the no-operation, and when the read program instruction is an instruction other than the instruction corresponding to the no-operation; , the addresses designated by the first and second address designating means are controlled and processed so as to be updated within the same clock cycle.

The supplementary explanation is as follows.

According to the conventional method described above, the pattern memory for storing test patterns and the memory for storing order information for reading out the test patterns (sequence information memory) must have the same capacity (same depth).

However, since most of the above order information is the order information "NOP" (see FIG. 2), which is an invalid instruction, the order information memory capacity was wasted.

Therefore, in the method of the present invention, only the information necessary to successively generate test pattern addresses is stored in the sequence information memory as compressed address type sequence information.

This will be explained using FIG. 3, which is a memory configuration diagram of an example of compressed address type order information.

FIG. 3a shows the conventional method, in which the addresses of the order information correspond one-to-one with the addresses of the test pattern.

On the other hand, FIG. 3b shows a compressed address type, for example, continuous order information
is represented by a single order information ``NOP until~''.

Therefore, the memory capacity for sequential information in this compressed address format is significantly reduced compared to the conventional method.
The sequence information memory uses a small-capacity, high-speed memory, and can be separated from the memory for storing test patterns, thereby achieving high speed and economical efficiency.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings.

FIG. 4 is a system configuration diagram of an embodiment of the test pattern readout control system according to the present invention.

Here, 1 is a pattern memory for storing (storing) test patterns, 2 is an address counter for specifying the address thereof, 3 is an order information memory for storing (memory) order information for reading test patterns,
4 is a program counter that instructs the address; 5 is a program counter that provides each control signal to the address counter 2 and program counter 4 according to the read order information; and in the case of a loop instruction, a program counter 6 The control unit 7, which gives instructions to the ``NOT until~'' command and also controls the entire operation, inputs the operand and the address counter 2 at the time of the ``NOT until~'' instruction.
a comparator which compares the values with the values of and sends a match signal to the control unit 5 if they match; 8 is a clock generator which generates a clock for the overall operation timing;
9 is a circuit under test.

In FIG. 4, only a part of the test pattern and order information of this method are shown as an example, but the operation thereof will be explained below according to the order information shown in FIG.

First, assume that in the initial state, both the program counter 4 and the address counter 2 indicate address #0.

At this time, the comparator 7 outputs its order information “NOP
The operand "2" of "until~" is compared with the value "0" of the address counter 2, and the control unit 5 is notified of the mismatch.

Since the output of the comparator 7 indicates a mismatch, the control unit 5 instructs the program counter 4 to hold the value, and instructs the address counter 2 to count up.

In this state, the pattern stored at address #0 of pattern memory 1 is read out as a test pattern (“10101001”) and
given to.

The next clock causes program counter 4
remains pointing to address #0 without changing its value, and address counter 2 counts up and points to address #1.

The comparator 7 receives the operand “#2” of the order information “NOP unil～” and the address counter 2.
is compared with "#1", which is the value of "#1", and again notifies the control unit 5 of the mismatch.

Since the output of the comparator 7 indicates a mismatch, the control unit 5 instructs the program counter 4 to hold the value again, and instructs the address counter 2 to count up.

In parallel with these operations, a test pattern (“11001010”) is read from address #1 of memory 1.

Furthermore, at the next clock, program counter 4
continues to hold its value and point to address #0, but address counter 2 counts up and points to address #2.

Again, the comparator 15 selects the operand “#2”
and the value “#2” of address counter 2,
Since they match, a match signal is sent to the control section 5.

Based on the coincidence signal, the control section 5 instructs the program counter 4 to count up, and also instructs the address counter 2 to count up.

In parallel with these, the test pattern (“00011011”)
is read from address #2 of pattern memory 1,
The signal is applied to the circuit under test 9.

At the next clock, program counter 4
indicates address #1, and address counter 2 indicates address #3.

When the control unit 5 recognizes that the order information "LOOP" is a loop instruction, it instructs the loop counter 6 to load "" of the loop number operand. It also instructs the program counter 4 to count up and also instructs the address counter 2 to count up.

At the next clock, program counter 4 will point to address #2, and address counter 2 will point to address #4. Thereafter, as described above, the value of the program counter 4 is held at address #2 until the value of address counter 2 indicates address #6, and the NOP operation (see FIG. 2) is repeated.

When the value of address counter 2 indicates address #6, this matches the operand "#6" of the NOP instruction, and a match signal is sent from comparator 7. Therefore, according to the instruction from controller 5, the next At this clock, the program counter 4 indicates address #3, and the address counter 2 indicates address #7.

Here, the controller 5 verifies the zero signal from the loop counter 6 based on the order information "LOOPEND" (loop end command), but in this case, since the count result of the loop counter 6 is not 0, the loop counter 6 is instructed to count down, program counter 4 is specified to load address #1, and address counter 2 is specified to load address #3, and at the next clock, the start of the loop is specified. Make it branch to .

At this time, the data #1 address and #3 address indicating the start position of the loop may be held as operands by the loop end instruction, or the data of the program counter 6 and address counter 2 may be stored as operands at the time the loop instruction is issued. The control unit 5 may temporarily store the value. After this, the same operation as described above is repeated.

In this way, even if the small-capacity order information memory 3 that stores compressed address-type order information is used, the order information before compression shown in FIG. The amount of hardware can be reduced, making it more economical and faster.

It is clear that such a test pattern readout control system can also be used for pattern generation sequence control in a memory tester and pattern generation in a logic tester.

〔Effect of the invention〕

As described in detail above, according to the present invention, the order information for reading test patterns can be compressed to about a few tenths of that in the conventional case in normal cases, and the order information memory that requires high speed can be compressed. Since it is possible to use a small-capacity device, this type of test equipment can be significantly improved in efficiency, speed, and economy.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of an example of a conventional pattern reading test device, FIG. 2 is a correspondence diagram of order information and operation contents, and FIG. 3 is a memory configuration diagram of an example of compressed address type order information. FIG. 4 is a system configuration diagram of an embodiment of the pattern reading test device according to the present invention. 1...Pattern memory, 2...Address counter, 3...Sequence information memory, 4...Program counter, 5...Control unit, 6...Loop counter,
7... Comparator, 8... Clock generator, 9... Circuit under test.

Claims (1)

[Claims] 1. Store various test patterns, their readout order information, and expected value patterns corresponding to each of the above test patterns, read out the test patterns according to the above order information, input them to the circuit under test, and then In a test device having a function of determining the acceptability of the circuit under test by comparing the output of the circuit under test with the expected value pattern corresponding to the test pattern, a first It includes a storage means, a first addressing means for generating and specifying a read address of the first storage means, and an instruction regarding control contents for the first addressing means and a storage location of an instruction to be executed next. a second storage means for storing program instructions; a second addressing means for specifying a read address of the program instructions with respect to the second storage means; When the instruction corresponds to Yon, the address specified by the first addressing means is
fixing the address specified by the second addressing means until it matches the address value indicated by the instruction corresponding to the no-operation, and when the read program instruction is an instruction other than the instruction corresponding to the no-operation; . A pattern reading test device comprising: control means for controlling the addresses specified by the first and second address specifying means to be updated within the same clock cycle.