JPS61253480A - Pattern generator - Google Patents

Abstract

PURPOSE:To enable the generation of a lengthy pattern, by memorizing only the address for changing points of a pattern to be generated. CONSTITUTION:A pattern address from a test sequence controller 1 is compared with the changing point address by a comparator 6 and the pattern is inverted with an FF circuit 7 as each changing point is detected so that the generation of a pattern can be done independently at each one pin unit. Thus this employs a system of memorizing only the address of changing points in a pattern to be generated into a pattern address memory 4 to reduce the capacity of the pattern memory drastically, thereby enabling the generation of a lengthy pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pattern generator, and particularly to a logic IC.
The present invention relates to a pattern generator that reduces the capacity of a memory for storing patterns of a test pattern generator for use in other applications.

[Background of the invention]

As a conventional method for generating test patterns for logic LSIs, pattern data to be generated is stored in a pattern memory in advance (a stored response pattern generator as disclosed in Japanese Patent Publication No. 53-59729 is known). There is.

However, in such a configuration, when a long pattern is generated, the memory increases approximately in proportion to the pattern length. In order to improve this problem, stored response pattern generators are equipped with loop and jump functions that allow them to repeatedly generate the same pattern. For this reason, the configuration becomes complicated and a large amount of memory is required.

[Purpose of the invention]

1. An object of the present invention is to provide a pattern generator capable of generating a long pattern with a simple configuration.

[Summary of the invention]

The present invention compares the pattern address from the test sequence controller with the changing point address using a comparator, and each time a changing point is detected, the pattern is inverted using a flip 70 knob, and pattern generation is performed independently for each pin. This is what I decided to do.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described using Figures O1 to O5.

Figure 1 is a block diagram showing one embodiment of the present invention.

The pattern generator of the present invention is controlled by a test sequence controller IK. The pattern address memory 4 stores the changing point address of the pattern, outputs the changing point address according to the address from the pointer 3, and outputs the changing point address to the comparator 6.
to the A input of Further, the address register 5 takes in the pattern address given from the test sequence controller 1 and gives it to the input of the comparator 60B. Comparator 6
compares the inputs of A and B to see if they match or do not match, and outputs a detection signal if they match. This signal causes flip-flop 7 to generate an output pattern of 0'' or 11'', and pointer 3 indicates an address to pattern address memory 4. Register 2 is a temporary holding register for outputting data from test sequence controller 1 to pointer 3. In addition, at the time of a jump instruction (branch instruction), a jump pattern memory 9 is provided to store the output pattern 17 immediately after the jump, and a register 8 for taking in and outputting the address and data for reading the memory and the 717 flip-flop 7 after the jump are provided. A jump controller 10 for controlling is provided.

Next, Figure 2 shows the correspondence between the change point addresses stored in the pattern address memory 4 and the pattern data generated from the pattern data memory 13 in an ordinary tester. Further, the read address of the pattern data memory 13 is outputted as a pattern address during testing from the test sequence controller 1 shown in FIG.

Figure 3 is an example of a timing chart when patterns are sequentially generated from the pattern address memory 4.

Figure 4 shows an example of the contents of the jump data memory 9 in Figure 1 and an example of a program when the test sequence controller 1 generates a jump pattern.

Figure 5 is a timing chart showing the operation of Figure 1 in the jump instruction program of Figure 24.

Next, in the case where the change point addresses shown in Figure 2 are stored, the case where patterns are sequentially generated will be described using Figures 1 to 5. The change point address is stored in advance from the test sequence controller 1 before the test. Register 2 contains the starting address Φ
D is included. The pointer 3 takes this in by the first clock 18 and stores it in the pattern address memory 4.
The pattern address memory 4 outputs the change point address 15 (AO) to the comparator 6. At the same time, the address register 5 receives the pattern address (A
O) is taken and applied to the comparator 60B input.

From this K, the comparator 6 detects that the two addresses to which this A-BK large input is input are AO (A input) - AO (B input), and sends a detection signal to the flip 70 knob 7 and pointer 3. Output. Therefore, next in 7 lip 70 tube 7,
Output turn 17 generates 1". At pointer 3,
The next address number O to 1 is incremented by +1. The same thing is done with the second clock, and the comparator 6 compares the changing point address 15 (AI) and the pattern address 16 (At) to detect the changing point.

As a result, the output turn 17 of the flip-flop 7 is inverted to @0'', and the output address of the pointer 3 is incremented by +1 from +1 to +2. Next, at the third clock, the change output from the pattern address memory 4 point address 1
5 becomes A4, and A2 is output as the pattern address 16, so the output of the comparator 6 becomes A+B (A4 + A2), and the detection signal of the change point is not generated. Therefore, the output cover pattern 17 is 0'' Similarly, at the fourth clock, since A=iyB (A44A3), the detection signal is not output, and the output cover turn 17 maintains the state of 0''. At the fifth clock, the pattern Address 16 becomes A4, and the output of comparator 6 is A-B (A4
-A4), and in order to detect the change point, the output turn 17 of the flip-flop 7 is inverted to the 11" state. At this time, the pointer 3 changes the output address from 2 to +3.
1 will be given. In this way, while comparing the change point address and the pattern address, each time they match, the output of the 717 push block 7 is inverted to obtain the output pattern 17.

Next, in the embodiment of Figure 1, a jump instruction (J MP
) occurs, the operation is shown in Figure 4.
This will be explained below using Figure 5.

With the first clock, pointer 5 outputs +0, and pattern address memory 4 outputs change point address 1.
5(AO) is applied to the comparator 608 input. At the same time, a pattern address (An) is output from the test sequence controller 1, taken into the address register 5, and passed through the pattern address line 16 to the comparator 60B.
given to the input. When the comparator 6 detects that the human inputs A and B match, it provides a detection signal to the 7-lip-flop 7. As a result, the first output pattern 17
11” is generated.

At the same time, the output of pointer 3 is also incremented by 1 from 0 to 1.

Next, the second clock causes the change point address 15 (AI
) is applied to the A input of comparator 6. Also, the next pattern address 1 is input to the comparator 60B input as in the previous cycle.
6(A1) is given. As a result, the comparator 6 detects a match and generates the second output turn "0". At the same time, as shown in the second cycle of the diagram f'5, since the current instruction is a Kachamp instruction (JMP), the test sequence controller 1
The pointer address (su2) after the jump is sent to.

With the third clock, the register 8 takes in the jump address JO and outputs data "1" corresponding to the jump pattern memory 9KJO.

Based on this data, the jump controller 10 outputs a reset signal to the flip-flop 7 only during the jump cycle using the jump control signal. On the other hand, at this time, pointer 3 takes in the output divided by 2 from register 2, outputs pattern address memory tK, and outputs change point address 1 from pattern address memory 4.
5 (A4) is applied to the comparator 60A input.

Also, from address register 5, pattern address 1
6 (A4) is applied to the comparator 60B input. Comparator 6
detects that the inputs of A and H match, and flips 7
A detection signal is output to the 0 knob 7, but when the jump is busy, the set signal from the jump controller 10 mentioned above has priority, so the pattern from the jump pattern memory 9 @
1" is given to the 7-rip 70 knob 7. If the read data of the jump pattern memory 9 is @0",
A reset signal is output to the 7 lip 70 knob 7, and 0'' is generated at the output pattern 17.Next, at the fourth clock, since the normal operation mode (NOP) is set, the pattern address memory 4 and the pattern The operation of comparing the contents of address 5 is repeated.The next jump from the fifth clock is performed in the same manner as the third jump.

As described above, according to the present invention, since only the address of the change point of the pattern to be generated is stored, the capacity of the conventional pattern memory can be significantly reduced, and a long pattern can be generated.

Note that loops such as repeated occurrence of patterns, jumps in the negative direction, etc. are also possible.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the amount of node wear and generate a long pattern.

Furthermore, not only is it easier to create pattern data for each bin, but it is also possible to reduce the time required to transfer test pattern data created by a computer or the like to a tester.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is an explanatory diagram showing storage of changing point addresses of pattern addresses in the present invention, and Figure 3 is a block diagram showing the pattern memory 4 shown in Figure 1.
Fig. 4 is a memory configuration diagram showing the contents of the jump data memory 9 shown in Fig. 1, and Fig. 5 is a timing chart based on the jump instruction program (processing timing chart). 1...Test sequence controller, 3'' pointer, 4...Pattern address memory, 5...Address register, 6...Comparator, 7...Flip controller 7', 8...・Register, 9...Jump pattern memory, 10...Jump controller.

Claims (1)

[Claims] a pattern address memory that stores only the address of the change point from 0 to 1 or from 1 to 0 in the pattern output from the test sequence controller; a comparison section that determines whether the change point address matches or does not match; an address generation section that supplies an address to the pattern address memory based on a detection signal and a clock that the comparison section outputs when both inputs match; and a branching section. A pattern memory that stores pattern data that is output when a command is issued, and a control signal that is generated based on a detection signal from the comparison section and pattern data from the pattern memory, and outputs 1 or 0 level pattern data. A pattern generator comprising a pattern output section.