JPH0762697B2 - Pattern generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generator, and more particularly, to pattern generation for reducing the capacity of a memory for storing a pattern of a test pattern generator for a logic IC. Regarding vessels.

[Background of the Invention]

As a conventional logic LSI test pattern generation method, there is known a stored response method pattern generator such as Japanese Patent Publication No. 53-39729 which stores pattern data to be generated in advance in a pattern memory. .

However, in such a structure, the memory increases in proportion to the pattern length when a large pattern is generated. In order to improve this inconvenience, the stored response type pattern generator has a loop or a jap function that can repeatedly generate the same pattern. Therefore, the structure is complicated and a large memory capacity is required.

[Object of the Invention]

An object of the present invention is to provide a pattern generator capable of generating a long pattern with a simple structure.

[Outline of Invention]

The present invention compares the pattern address from the test sequence controller and the change point address with a comparator, and every time the change point is detected, the pattern is inverted by the flip-flop, and the pattern generation is independently performed for each pin. It's something that you do.

Example of Invention

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of the present invention.
The pattern generator of the present invention is controlled by the test sequence controller 1. The pattern address memory 4 stores the change point address of the pattern, outputs the change point address according to the address from the pointer 3, and outputs the change point address to the comparator 6.
To the A input of. Further, the address register 5 fetches the pattern address given from the test sequence controller 1 and gives it to the B input of the comparator 6. Comparator 6
Compares the inputs of A and B for a match or a mismatch, and outputs a detection signal if they match. By this signal, the flip-flop 7 generates an output pattern of "0" or "1", and the pointer 3 points the address to the pattern address memory 4. Register 2 is test sequence controller 1
It is a temporary holding register for outputting the data from the pointer to the pointer 3. At the time of a jump instruction (branch instruction), a jump pattern memory 9 for storing the output pattern 17 immediately after the jump is provided, and a register 8 for fetching and outputting an address and data for reading the memory and a flip-flop 7 after the jump are provided. A jump controller 10 for controlling is provided.

Next, FIG. 2 shows the correspondence between the change point address stored in the pattern address memory 4 and the pattern data generated from the pattern data memory 13 in the normal tester. The read address of the pattern data memory 13 is output from the test sequence controller 1 of FIG. 1 as a pattern address at the time of testing.

FIG. 3 is an example of a timing chart when patterns are sequentially generated from the pattern address memory 4.

FIG. 4 shows an example of the contents of the jump data memory 9 of FIG. 1 and an example of a program when the test sequence controller 1 generates a jump pattern.

FIG. 5 is a timing chart showing the operation of FIG. 1 in the program of the jump instruction of FIG.

Next, in the case where the change point address shown in FIG. 2 is stored, the case where sequential patterns are generated will be described with reference to FIGS. The change point address is stored in advance from the test sequence controller 1 before the test. Register # 2 has the address #D at start
Has been incorporated. The pointer 3 takes in this by the first clock 18, outputs address #O to the pattern address memory 4, and outputs the change point address 15 (A0) from the pattern address memory 4 to the A input of the comparator 6. At the same time, the address register 5 receives the pattern address (A0) from the test sequence controller 1 and supplies it to the B input of the comparator 6. As a result, the comparator 6
Detects that the two addresses input to A and B are A0 (A input) = A0 (B input), and outputs a detection signal to the flip-flop 7 and the pointer 3. Therefore,
Next, in the flip-flop 7, the output pattern 17 generates "1". In the pointer 3, the next address # 0 to # 1
It is incremented by +1. The same operation is performed with the second clock, and the comparator 6 compares the change point address 15 (A1) with the pattern address 16 (A1) to detect the change point. As a result, the output pattern 17 of the flip-flop 7 is inverted to "0", and the output address of the pointer 3 is incremented by 1 from # 1 to # 2.
To be done. Next, at the third clock, the change point address 15 output from the pattern address memory 4 becomes A4,
Since A2 is output as the pattern address 16, the output of the comparator 6 becomes A ≠ B (A4 ≠ A2), and the detection signal of the change point is not generated. Therefore, the output pattern 17 holds the state of "0". Similarly, A ≠ B at the fourth clock
Since (A4 ≠ A3), the detection signal is not output and the output pattern 17 holds the state of “0”. In the fifth clock,
The pattern address 16 becomes A4, and the output of the comparator 6 is A =
The output pattern 17 of the flip-flop 7 is inverted to the state of "1" in order to detect the change point since it becomes B (A4 = A4). At this time, the pointer 3 shifts the output address from # 2 to # 3
1 is done. In this way, while comparing the change point address and the pattern address, the output of the flip-flop 7 is inverted each time they match and the output pattern 17 is obtained.

Next, an example of the case where the jump instruction (JMP) occurs in the embodiment of FIG. 1 will be described below with reference to FIGS. 4 and 5. # 0 is output to the pointer 3 by the first clock and the pattern address memory 4
From, the change point address 15 (A0) is given to the A input of the comparator 6. At the same time, the pattern address (A0) is output from the test sequence controller 1, taken into the address register 5, and given to the B input of the comparator 6 via the pattern address line 16. The comparator 6 receives this input
When it is detected that A and B match, a detection signal is given to the flip-flop 7. As a result, "1" is generated in the first output pattern 17. At the same time, the output of the pointer 3 is also incremented from # 0 to # 1. Next, at the second clock, the change point address 15 (A1) of the pattern address memory 4 designated by the pointer 3 is given to the A input of the comparator 6. The next pattern address 16 (A1) is applied to the B input of the comparator 6 as in the previous cycle. As a result, the comparator 6 detects the coincidence and generates the second output pattern "0". At the same time, as shown in the second cycle of FIG. 5, since the current instruction is a jump instruction (JMP), the test sequence controller 1
Is the pointer address (#
2) is sent. Register 8 by the 3rd clock
Takes in the jump address J0 and outputs the data "1" corresponding to J0 to the jump pattern memory 9. And
In the jump controller 10, based on this data,
The jump control signal outputs a set signal to the flip-flop 7 only during a jump cycle. On the other hand, at this time, the pointer 3 takes in the output # 2 from the register 2 and outputs it to the pattern address memory 4, and from the pattern address memory 4, the change point address 15 (A4) is given to the A input of the comparator 6. Further, the pattern address 16 (A4) is given to the B input of the comparator 6 from the address register 5. The comparator 6 detects that the inputs of A and B are the same and outputs a detection signal to the flip-flop 7, but at the time of jump, the jump controller 10 described above is used.
Since the set signal from 1 has priority, the pattern "1" from the jump pattern memory 9 is given to the flip-flop 7. When the read data of the jump pattern memory 9 is "0", the reset signal is output to the flip-flop 7 and the output pattern 17 is "0". Next, in the fourth clock, the normal operation mode (NOP) is set, so the pattern address memory 4 and the pattern address 5
The operation of comparing the contents of is repeated. In the next jump from the fifth clock, the same operation as in the third jump is performed.

As described above, according to the present invention, since only the address of the change point of the pattern to be generated is stored, the capacity of the conventional pattern memory can be significantly reduced, and a long pattern can be generated.

It should be noted that loops such as repeated generation of patterns and jumps in the negative direction are also possible.

〔The invention's effect〕

As described above, according to the present invention, the amount of hardware can be reduced and a long pattern can be generated. Further, not only the pattern data can be easily created for each pin, but also the transfer time of the test pattern data created by a computer or the like to the tester can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the change point address storage of a pattern address in the present invention, and FIG. 3 is a pattern memory 4 shown in FIG.
4 is a timing chart when the patterns are sequentially generated, FIG. 4 is a memory configuration diagram showing the contents of the jump data memory 9 shown in FIG. 1, and FIG. 5 is a timing chart of the processing based on the jump instruction program. 1 ... Test sequence controller, 3 ... pointer, 4 ... pattern address memory, 5 ... address register, 6 ... comparator, 7 ... flip-flop, 8 ...
... register, 9 ... jump pattern memory, 10 ... jump controller.

Claims (1)

[Claims] 1. A pattern generation for use in a test device for judging pass / fail of an IC under test by sequentially supplying an input pattern of the IC under test and sequentially comparing an output from an output pin of the IC under test and an expected value pattern. In the instrument, the first memory that stores only the address that is the change point of the input pattern and the expected value pattern is compared with the pattern address that is output from the test sequence controller and the address that is the change point of the first memory. Comparing means for detecting the coincidence, address generating means for giving an address to the first memory based on a detection signal from the comparing means, and a second pattern storing a pattern output together with a branch instruction. The output of the memory is inverted by the detection signal from the comparison means, and the control signal is generated based on the pattern from the second memory. Ri pattern generator characterized by comprising an output means for outputting a pattern of logic 1 or 0.