JPH02103643A - Interruption generation circuit for debug - Google Patents

Abstract

PURPOSE:To efficiently make debugging by previously designating the address range of a functional routine to be verified in a microprogram and generating interruption when the designated address range is executed. CONSTITUTION:This interruption generation circuit is provided with a controlling storage 1, instruction register, execution controlling section 3, comparing address registers 5 and 6, comparator circuits 7 and 8, arithmetic circuit 9, and control circuit 10. By respectively storing necessary addresses in the comparing address registers 5 and 6 and designating a necessary mode to the control circuit 10, interruption is generated under the address range conditions of a microprogram and two-point address conditions. Therefore, a strong debugging means is obtained and the debugging efficiency can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debugging interrupt generating circuit, and more particularly to a debugging interrupt generating circuit provided in a central processing unit for verifying a microprogram.

[Conventional technology]

Conventionally, a method for verifying a microprogram has been to run the microprogram and test whether predetermined processing is performed without error even if an interrupt signal is applied from the outside during execution.

[Problem to be solved by the invention]

However, in the conventional microprogram verification method described above, it is difficult to generate an interrupt in synchronization with the execution of a specific function of the microprogram, and it is difficult to verify a microphone program that corresponds to various timings of interrupt generation. The problem is that it is difficult to

An object of the present invention is to provide a debugging interrupt generation circuit that can generate an interrupt when the specified address range is executed by specifying in advance the address range of a functional routine to be verified in a microprogram. .

[Means to solve the problem]

The debugging interrupt generation circuit according to the present invention is a processing device controlled by a microprogram stored in a control memory. first and second conveyor address storage means for storing the control memory address and first address data stored in the first conveyor address storage means each time a microprogram is executed; a first comparison means for comparing; and a second comparison means for comparing the control storage address and second address data stored in the second conveyor address storage means each time a microprogram is executed; arithmetic means for calculating the output of the first comparing means and the output of the second comparing means and generating the result of the calculation as an interrupt request signal; the first and second comparing means; and the calculating means. and means for controlling.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

The debugging interrupt generation circuit according to this embodiment has control a:l
E-memory 1. Instruction register 2. Execution control unit 3. Conveyor address registers 5 and 6. Comparison circuits 7 and 8. Arithmetic circuit 9. and a control circuit 10.

The microprogram is stored in control memory 1, and the microinstruction at the address specified by line 310 in control memory 1 is read and stored in instruction register 2.
is stored in The instructions read into the instruction register 2 in this manner are supplied to the execution control section 3, where they are decoded and executed. The address of the next instruction to be executed is generated in the execution controller 3 and applied to the control store 1 via line 310, which again reads the next instruction into the instruction register 2 and thus the control store 1. Each instruction of the stored microprogram is read out and executed one after another according to the program.

Now, this embodiment has three unique modes.

Each of these modes is specified by a mode designation signal supplied from a console (not shown) to the control circuit 10 via line 110, and the control circuit 10 uses the comparison circuit 7. Comparison circuit 8. and the arithmetic circuit 9 are controlled as shown below.

First, the comparison circuit 7 compares the contents supplied to the control memory 1 via the line 310 (this is referred to as C) and the contents of the conveyor address register 5 (this is referred to as A1), and according to the comparison result, " Outputs “1” or “0”, but
This result is given by the control signal 178 from the control circuit 10.
According to the designation of , it changes as shown in FIG. 2 depending on the mode.

That is, in the first mode, when the content C supplied to the control memory 1 via the line 310 and the content A1 of the conveyor address register 5 are equal (in the case of C-AI).
A logic "1" is outputted to the output signal, and a logic "0" is outputted when they are not equal (when C≠A1). Also, in the second and third modes, when the content C supplied to the control store 1 via line 310 is greater than or equal to the content A1 of the conveyor address register 5 (C>A
1), outputs logic “1” when it is small (C<
(at the time of AI), a logic "0" is output.

Similarly, the comparison circuit 8 connects the control memory 1 via line 310 to the control memory 1.
The contents supplied to the conveyor address register 6 are compared with the contents of the conveyor address register 6 (this is referred to as A2), and "1" or '0' is output according to the comparison result, but the method of giving this result is determined by the control circuit 10. The control signal 178 changes depending on the mode as shown in FIG. 2. That is, in the first mode, logic "1" is output when C-A2, and logic "0" is output when C≠A2. ′ is output. Further, in the second mode and the third mode, a logic "1" is output when C<A2, and a logic "0" is output when C>A2.

Next, the arithmetic circuit 9 logically synthesizes the output of the comparator circuit 7 (which is designated as P) and the output of the comparator circuit 8 (which is designated as Q) to generate an interrupt generation factor signal 930. The method of logic synthesis changes depending on the designation of the control signal 109 from the control circuit 10 as shown in FIG. 2 for each mode.

That is, in the first mode, the interrupt generation factor signal is generated by the OR of P and Q, in the second mode, by the AND of P and Q, and in the third mode, by the NAND logical operation of P and Q. do.

As is clear from the above, according to this embodiment, when the first mode is specified from the console via the line 110, when C-Al or C-A2 is established, the second mode is also specified.
When a mode is specified, if AI<C<A2 is established, and a third mode is specified, C<AI or C
>A2 is established, the interrupt generation factor signal 930 becomes “
1″.

This interrupt generation factor signal 930 is supplied to the execution control unit 3, and is logically summed with other interrupt generation factors therein. When the interrupt generation factor signal 930 becomes logic "1", an interrupt occurs. be done.

As described above, according to this embodiment, by storing the necessary addresses in the conveyor address registers 5 and 6, and specifying the necessary mode in the control circuit 10, the address range of the microprogram, which was previously impossible, is achieved. In addition, it is possible to generate an interrupt under a two-point address condition.

〔Effect of the invention〕

As described above, according to the present invention, in order to test whether a predetermined operation is performed even if an interrupt occurs during the execution of a microprogram, the An interrupt can be generated when any one of these is executed, making it possible to provide a powerful debugging means that was not possible with the prior art, and making the debug knob more efficient.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention;
FIG. 2 is a diagram for explaining the operation of the circuit used in this embodiment. DESCRIPTION OF SYMBOLS 1... Control memory, 2... Instruction register, 3... Execution control part, 5, 6... Conveyor address register, 7
．． 8... Comparison circuit, 9... Arithmetic circuit, 10... Control circuit.

Claims (1)

[Scope of Claims] 1. In a processing device controlled by a microprogram stored in a control memory, address data for comparison with a control memory address supplied to the control memory is stored in first and second addresses. The first to be stored as data
and a second conveyor address storage means, and a first comparison means for comparing the control storage address and the first address data stored in the first conveyor address storage means each time a microprogram is executed. a second comparison means that compares the control storage address with the second address data stored in the second conveyor address storage means each time a microprogram is executed; and an output of the first comparison means. and an output of the second comparing means, and generating the result of the calculation as an interrupt request signal; and a control means for controlling the first and second comparing means and the calculating means. A debugging interrupt generation circuit characterized by having the following features.