JPS63197246A - Microprogram controller - Google Patents

Abstract

PURPOSE:To omit the addition of a debug-only routine by checking whether an optional register is set at the expected value or not in the form of a hardware operation while each microinstruction of a microprogram is executed and then stopping the run of the microprogram when the register is set at the expected value. CONSTITUTION:The original executing order A B C of a microprogram is changed into another order A Z B Z C when the bus output instructions Z are put between microinstructions. These instructions Z, however, just function to output an optional register to a bus and does not change the overall hardware state. Under such conditions, an arithmetic circuit 11 compares the bus outputs with each other in a mode designated by a console. Furthermore the AND processing is performed by an AND gate with an F/F 6. Thus logic 1 is outputted to a signal line 113 only when the bus output obtained by the instruction Z serves as a comparison object and satisfies the designated comparison conditions. The logic 1 is supplied to an execution control part 5 as a microprogram stop signal.

Description

[Detailed description of the invention] Bold! [1] The present invention relates to a microprogram 1IJIIl device,
In particular, it relates to a microprogram controller that performs depacking functions.

BACKGROUND TECHNOLOGY In general, microprogram control devices are capable of temporarily halting the execution of a program at any pre-specified address in the t111m memory where the microprogram is stored, in order to facilitate debugging of the microprogram. It has functions.

That is, it generally includes a comparison address register that stores address data for comparison with the control memory address supplied to the i, IItll memory, and each time a microprogram is executed, the contents of this comparison address register and the control memory address supplied to the vll memory are compared. It has a function that can compare the two and stop the execution of the microprogram if a match is detected.

When debugging, 1lJltl, which stores the microinstructions that should temporarily suspend the execution of the microprogram.
A storage address is input from, for example, a console, stored in a comparison address register, and then the microprogram is started. Then, when the microphone program stops at this specified instruction (1,!I tall storage address) using the above function, the microprogram processes by checking the contents of various registers and other internal states in this state. Check whether it is working as desired so far. When this confirmation process is completed, the next address to be stopped is specified again as needed, and the program can be restarted from the current stopped address (or any other arbitrary address). Such a function is an effective means for debugging.

The conventional microprogram control device described above, for example, when debugging a specific routine under conditions where the value of a certain register becomes a value within a certain range, it is necessary to know in advance how many times the value will reach that value. If there is, the address of a specific routine [can be stopped]. However, in general, microprograms cannot be predicted because they perform complex operations depending on the order of rough 1-ware instructions or external factors (including v1 from input/output devices, etc.), and in reality, stopping under such conditions is impossible. Can not.

Therefore, conventional microprogram control devices are designed specifically for debugging, such as branching to a unique address (or executing an instruction that stops the microprogram) when the value of one register in a specific routine reaches a certain range. Equivalent functionality is achieved by adding the following routine.

However, the above is just a microb [C that is not executed equally at all timings of 1-gram execution, and has the disadvantage that it is necessary to add debugging routines each time where it is considered to be the minimum necessary.

OBJECTS OF THE INVENTION An object of the present invention is to provide a microprogram control device that does not require the addition of a debugging routine and can equally stop a microprogram at all timings of microprogram execution.

Structure of the Invention According to the present invention, a microprogram & The control device includes a bus output instruction register for storing a microinstruction for deriving the contents of a predetermined register in the microinstruction execution means to an internal bus, and one of the microinstruction register and the bus output instruction register. selection means for alternately selecting and supplying microinstructions to the microinstruction execution means; first comparison means for comparing data on the internal bus with a predetermined first value; 11. A second comparing means for comparing the data of 1 with a predetermined second value; and stopping the execution of the microinstruction executing means in accordance with the comparison results of both the first and second comparing means.11. A microprogram device is obtained, which is characterized in that it has a microprogram IllI control means for controlling the microprogram.

11] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a daily schedule showing an embodiment of the present invention.

The microphone D program υ1611 device of this embodiment has control memory 1. Instruction register 2. Bus output instruction register 31 selection circuit 4. Execution u control unit 5. flip-flop (hereinafter referred to as
(abbreviated as F/F)6. Comparison data registers 7 and 8
．． Comparison circuit 9 and 10° performance circuit 11. Control circuit 12
and an AND gate 13.

Next, the operation of the microprogram-based tIl device of this embodiment configured as described above will be explained.

The microprogram stored in the control memory 1 is read out to the instruction register 2, selected by the selection circuit 4, and supplied to the execution control section 5 to be executed. In this case, F/
F6 is logically turned ON and J3 is selected, and the selection circuit 4 selects the microinstruction stored in the instruction register 2. The F/F 6 has a function of inverting its value every clock cycle, that is, every time a microinstruction is executed, as shown in the time chart of FIG. Therefore, the microinstruction in instruction register 2 is executed υ)t[! After being executed in the unit 5, the F/F 6 becomes logic "1n," and the selection circuit 4 executes a microinstruction for selecting the contents of the bus output instruction register 3 and outputting the contents of any register to the internal bus. It will be supplied to the control unit 5 and executed.

Now, this embodiment has three unique debugging modes. 1i111!1 circuit 12 is connected to comparison circuit 9.1 by designation from a console (not shown). The comparator circuit 10 and the arithmetic circuit 11 are ¥Alfl as shown below.

First, the comparison circuit 9 compares the bus output data (this is referred to as BLJS) via the line 105 with the comparison data register 7.
(this is set as Dl) and outputs 1" or "On according to the result of this comparison, but the method of giving this result is as follows:
Accordingly, it changes as shown in FIG. That is, in the first mode, the logic level "111" is output when BtJS-Dl, and "0" is output when BUS≠01. Furthermore, in the second mode and the third mode, a logic level "1'" is output when BUS≧D1, and a logic level "0" is output when BLIS<DI.

Similarly, the comparison circuit 10 connects the BUS and the comparison data register 8.
(this is set as Dl), and in the first mode, when BtJS=02, a logic level "1" is output,
Outputs “0” when BUS+D2. Further, in the second mode and the third mode, the logic level 111 II is output when Bus';Dl, and "0"' is output when Bus>Dl.

Next, the arithmetic circuit 11 logically synthesizes the output of the comparison circuit 9 (this is designated as P) and the output of the comparison circuit 10 (this is designated as Q) to generate the program stop factor signal 110.
The method of logic synthesis is 1llltI from the control circuit 12.
1 signal 212 causes a change as shown in FIG. That is, P orQ in the first mode.

PandQ in the second mode and Pna in the third mode
ndQ is output.

As is clear from the above, according to this embodiment, when the first mode is specified from the console, the program stop cause signal 11 is set to BtJS-[)1 or Bus-Dl.
0 becomes 1”. Similarly, when the second mode is specified, D
When 1≦BtJS≦D2, or when the third mode is specified, the program stop factor signal 110 becomes “1”.

On the other hand, instruction register 2 is held when F/F6 is logic "1", and υl'm memory 1 is held only when logic u On.
Stores microinstructions from

The above operation will be explained with reference to the timing chart shown in FIG. 2. When the F/F 6 is at logic "O" and the microinstruction A is stored in the instruction register 2, execution 1.
Microinstructions are supplied to the 1111 unit 5 and executed. As a result, the microinstruction B to be executed next is read out from the lbl_tll memory 1 and stored in the instruction register 2. At the same time, the F/F 6 is inverted to logic "1", so that the next execution! IJIII section 5 is supplied with the microinstruction Z stored in the bus output instruction register 3 and executed.

Thereafter, as the same operation is repeated, instead of the original execution of the normal microprogram A→B-+C, a bus output instruction Z is inserted between each microinstruction, and the sequence is A-+Z→B→ An execution like Z→C is realized. However, the bus output instruction Z only outputs an arbitrary register to the bus and does not change any hardware state.

During the above operation, the arithmetic circuit 11 compares the bus output under the mode specified from the console, but since the AND gate 13 performs AND processing with F/F6, the signal line 113 is connected to the bus output by the bus output command Z. Logical only if the output is a comparison pair and satisfies the specified comparison condition.
1'' is output and supplied to the execution control section 5 as a microprogram stop signal.

Note that the bus output command register 3. It is assumed that the comparison data register 7 and the comparison data register 8 are supplied in advance from a console (not shown) with a microinstruction for instructing the bus output of the comparison target register and comparison data and stored therein.

As explained above, according to the present invention, during the execution of each microinstruction of a microprogram, it is checked as a hardware operation whether or not an arbitrary register has reached the expected value. By stopping the microblock program when the microprogram is running, it becomes unnecessary to add a conventional debugging routine, and furthermore, it becomes possible to provide a powerful debugging method that can equally stop the microprogram at all timings of microprogram execution. This has the effect of making debugging more efficient.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the blocks in FIG. 1, and FIG.
FIG. 3 is a diagram showing the relationship between the program stop mode and the output of each circuit in the cause block. Explanation of symbols of main parts 1... Control storage unit 2... Instruction register 3... Bus output instruction register 4... Selection circuit 5... ...Execution control unit 7.8...Comparison data register 9.10...
... Comparison circuit 11 ... Arithmetic circuit 12 ... Control circuit

Claims (1)

[Claims] A microprogram control device for an information processing device, comprising a microinstruction register that stores microinstructions read from a control storage unit, and microinstruction execution means that controls execution according to the microinstructions, the microinstruction execution means a bus output instruction register for storing a microinstruction for deriving the contents of a predetermined register in the means to an internal bus; and the microinstruction execution means by alternately selecting one of the microinstruction register and the bus output instruction register. selection means for supplying a microinstruction to a predetermined second value; first comparison means for comparing data on the internal bus with a predetermined first value; A microprogram characterized in that it has a second comparison means for comparing a value with a value, and a control means for stopping execution of the microinstruction execution means according to the comparison results of the first and second comparison means. Control device.