JPS63226778A - Memory device - Google Patents

Abstract

PURPOSE:To simplify the constitution of a control means for an image part by allowing a microprogram to execute control or timing generation. CONSTITUTION:The control means 2 of the image memory 1 consists of a microsequencer 20, a microprogram counter 21, a microprogram memory part 22, a pipe-line register 23, and so on. The microsequencer 20 fetches various status to judge the start or end of processing and controls the program counter 21 to start the microprogram stored in the microprogram memory part 22. The microprogram executes control in various processing and the switching of timing generation by jumping operation to a prescribed address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device for storing image information in the field of image processing, and particularly to simplifying the configuration of a control means of an image memory section.

[Summary of the Invention] The present invention provides a memory device for storing image information in the field of image processing, comprising a control means equipped with a microprogram,
The configuration of the control means is simplified by simultaneously controlling a large number of control signals and generating the control timing.

[Prior Art] A frame memory is conventionally known as a memory device that uses a dynamic RAM (random access memory) and stores image information in image processing.

FIG. 5 is a block diagram showing a schematic configuration of a conventional frame memory. The frame memory is accessed by various processors and processing circuits that perform image processing, and is further accessed by an image display device (monitor display). In addition, refresh control must be performed to control the dynamic RAM. In each of these access processes, even if the control signal of the image memory section 100 is the same, it is often necessary to perform different timing control for each process. For this reason, conventionally,
Timing generation circuit 101 that generates necessary timing
a, 10 lb, 101c... are provided for each type of processing, and switching circuits 102a, 102b, 102c
The image memory section was controlled by switching control signals with the same name having different timings depending on each of them. In addition, as related technology, Japanese Patent Application Laid-Open No. 61-13
There is an access address generation circuit for an image memory disclosed in Japanese Patent No. 289.

[Problems to be Solved by the Invention] However, the above-mentioned conventional control processing for the image memory section of the frame memory is characterized by a large number of types, and it is necessary to assemble timing generation logic using hardware for each processing. This not only makes the circuit complicated and difficult to design, but also makes it difficult to see the circuit diagram.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a memory device for storing image information in which the configuration of the control means of the image memory section is simplified.

[Means for Solving the Problems] The configuration of the memory device of the present invention for achieving the above object includes an image memory section for storing input image information and a microprogram, and the microprogram stores the image memory. The present invention is characterized by comprising a control means for controlling the control section and generating the control timing.

[Operation] According to the present invention, the control of the image memory unit for each type of processing and the timing generation thereof are performed by a microprogram without using hard-wired logic. In the microprogram, control for each type of processing and switching of timing generation are executed by jumping to a predetermined address. Furthermore, by using a microprogram, it is possible to simultaneously control a large number of control signals at high speed.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The memory device of this embodiment can be roughly divided into an image memory section 1 that stores image information input via a pass line from a CPU that performs external image processing, and an image memory section 1 that stores image information input from a CPU, a monitor display device, etc. and control means for controlling access based on the access request.

Since image information handled in image processing requires a large capacity and requires high-speed access, a dynamic RAM is generally used as the storage element of the image memory section l.
Moreover, a plurality of frame configurations may be used depending on the application.

The control means 2 includes a micro sequencer 20. Micro program counter 21. Microprogram memory section 22
．． It is composed of a pipeline register 23 and the like. The micro sequencer 20 determines the start and end of processing by taking in various statuses, and the program counter 21
to start the microprogram stored in the microprogram memory section 22. The execution address of the microprogram in the microprogram memory section 22 is indicated by the counter value of the program counter 21, and is normally incremented by +1 each time one is executed, but if there is a jump instruction, the value specified there The counter value is changed and the execution address is branched to it. The instructions in the microprogram memory section 22 are sequentially set in the pipeline register 23. Although the pipeline register is not indispensable, the pipeline register 23 divides the micro operations within one clock (or unit time) into a range where there is no problem in controlling them simultaneously, and executes multiple instructions in a flow process. This is preferable because it speeds up the processing. The above processing results are various control signals (a) such as RAS and CAS signals in the dynamic RAM.

(b) is output to the image memory section 1 or the like.

FIG. 2 is an explanatory diagram of the configuration of the microprogram. This example shows a case where two control signals (a) and (b) are output at different timings and in different orders in a plurality of processes (1), (2), . . . . Address 1 of the microprogram memory stores an instruction to determine whether or not to execute process (1), and a jump instruction to branch to the first address 6 of the next process (2) if no (NO). has been done. The output commands of control signals (a) and (b) in process (1) are stored in addresses 2 to 5, and if the execution time of one address is one clock, the commands are output according to the required timing. The output content at each address may be determined from the output state within the clock. FIG. 3 is a timing chart showing an example of the timing of control signals (a) and (b). In order to execute the process (1) corresponding to this diagram, (a)=
0. (b) Corresponding to -0, there is an output instruction (0, 0) at address 2, and (a)=1 at clock CP2.

(b) Corresponding to o, the output command (1, 0) is placed at address 3, and similarly, the output command (o, H) is placed at address 4 (5).
The output command at address (0, 0) is stored.

Subsequently, at address 6, a judgment instruction for determining whether to execute process (2) or not, and a jump instruction for branching to the next process (3) if not, are stored. In addition, the process in Figure 3 (2
) Corresponding to CPI to CP4 of the timing chart,
The (0,0) output instruction is at address 7, and (0,0) is at address 8.
The output command 1) is stored at address 9, the output command (1, 1) is stored at address 9, and the output command (1, 0) is stored at address A. Thereafter, the processing contents starting from process (3) are stored in the same manner.

FIG. 4 is a flowchart for explaining the operation in this embodiment. When the microprogram is started, it is first determined whether "Execute process (1)?J" or not.
If YES, “execute process (1)” and, for example,
At the timing of process (1) in the figure, control signals (a), (b)
) is output. In the above judgment, if NO, branch to the judgment "Execute process (2)?" If YES, as above, execute process (2), and if No, branch to the next process judgment. . Which process to execute can be specified by reflecting the request from the access source in the status, etc., and switching between processes is executed by a jump instruction.

In the above, even if there is a change in the processing content, there is no need to change the wiring, which is difficult as in hard-wired logic, and it is only necessary to change the microprogram. In addition, even if the image memory sections are different, if the configuration is configured so that the maximum number of control signals can be output, the hardware of the control means will be fixed without needing to be changed, and only the microprograms will be able to correspond to each one. It gets better just by storing it. Furthermore, since the hardware is not involved in timing generation, the circuit is simple. on the other hand,
The microprogram itself has only three types of instructions, and timing generation can be adjusted by the number of processing steps.Hardwired logic can simplify complex processing.

It goes without saying that the present invention is not limited to the above-described embodiments, and can be applied in various ways and implemented in accordance with the spirit of the present invention. In the above embodiment, only the output of the control signal has been described, but it may also be incorporated in a part of the microprogram for controlling the image memory unit.

Effects of the Invention] As is clear from the above description, the memory device of the present invention provides the following effects.

(+) Since the control or timing generation is performed by a microprogram, the circuit that generates the control timing is fixed.

(2) The circuit becomes simpler and the number of parts decreases.

(3) Therefore, the circuit diagram becomes simpler and easier to understand.

(4) Changes in debugging and processing can be handled by changing the microprogram, making changes easy.

(5) Hard-wired logic with fewer types of instructions can simplify complex processing.

(6) Therefore, no special tools are required for programming or debugging.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the configuration of a microprogram, FIG. 3 is a timing chart showing an example of timing occurrence, FIG. 4 is a flowchart for explaining the operation, and FIG. FIG. 5 is a block diagram showing a schematic configuration of a conventional frame memory. I... Image memory section, 2... Control means, 22...
Microprogram memory section. 2 艷 1 Wholesale 1000 years old 1 da l Kufu mouth, 7 diagrams Fig. 1 Micro program 8 oars υ t Light part Fig. 2 = Quantity control tie Q'7゛υ generation child Fig. 3 Flowchi γ- Fig. 4 Conventional g11 n 701. Figure 5

Claims (1)

[Claims] A memory device comprising: an image memory unit that stores input image information; and a control means that includes a microprogram, controls the image memory unit using the microprogram, and generates control timing. .