JPH04140851A - Diagnostic system for information processor - Google Patents
Diagnostic system for information processorInfo
- Publication number
- JPH04140851A JPH04140851A JP2264143A JP26414390A JPH04140851A JP H04140851 A JPH04140851 A JP H04140851A JP 2264143 A JP2264143 A JP 2264143A JP 26414390 A JP26414390 A JP 26414390A JP H04140851 A JPH04140851 A JP H04140851A
- Authority
- JP
- Japan
- Prior art keywords
- address
- instruction
- execution
- executed
- microinstruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims description 6
- 238000002405 diagnostic procedure Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000003745 diagnosis Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は情報処理装置の診断方式に関し、特にマイクロ
プロセッサが実行した命令実行アドレスをトレースする
情報処理装置の診断方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a diagnostic method for an information processing device, and more particularly to a diagnostic method for an information processing device that traces the execution address of an instruction executed by a microprocessor.
従来の情報処理装置の診断方式において、マイクロプロ
セッサがマイクロ命令実行アドレスを制御記憶部に出力
し、制御記憶部からのマイクロ命令をマイクロプロセッ
サが実行し、マイクロプロセッサからの命令実行アドレ
スを記憶手段ですべて記憶するという方式がある。In a conventional diagnosis method for information processing equipment, a microprocessor outputs a microinstruction execution address to a control storage section, the microprocessor executes the microinstruction from the control storage section, and the instruction execution address from the microprocessor is stored in a storage means. There is a way to memorize everything.
上述した従来の情報処理装置の診断方式では、記憶手段
の記憶容量の制限により、記憶できる範囲が直前に実行
されたマイクロプログラムアドレス少量に限られてしま
い、また、マイクロプログラムの処理によっては、命令
の実行アドレスがループするために、必要とするマイク
ロプログラムアドレスの記憶ができないことがあり、マ
イクロプログラムのデパックや障害解析等に十分な効果
を発揮できないという欠点がある。In the above-mentioned conventional diagnostic method for information processing devices, due to the limited storage capacity of the storage means, the range that can be stored is limited to a small number of microprogram addresses that were executed immediately before, and depending on the processing of the microprogram, instructions may be Since the execution address of the microprogram loops, it may not be possible to store the required microprogram address, which has the disadvantage that it cannot be sufficiently effective for microprogram depacking, failure analysis, etc.
本発明の情報処理装置の診断方式は、マイクロプロセッ
サか実行するマイクロ命令実行アドレスを一時記憶する
アドレスラッチと、制御記憶部から出力され現在実行中
のマイクロ命令より１ステップ前に実行され前記アドレ
スラッチが記憶の前実行アドレスに１加算した予測アド
レスを出力する加算器と、前記マイクロ命令実行アドレ
スと前記予測アドレスとを比較し不一致のときアドレス
不一致信号を出力する比較器と、前記アドレス不一致信
号によりライト指示とアドレス加算指示とを出力するラ
イトタイミング制御部と、前記アドレス加算指示により
１加算したアドレスを出力するアドレス制御部と、前記
ライト指示と前記アドレスとにより示される番地に前記
前実行アドレスを記憶する記憶部とを有する。A diagnostic method for an information processing device according to the present invention includes an address latch that temporarily stores an execution address of a microinstruction to be executed by a microprocessor, and an address latch that is output from a control storage unit and executed one step before the currently executed microinstruction. an adder that outputs a predicted address obtained by adding 1 to the previously executed address stored in memory; a comparator that compares the microinstruction execution address and the predicted address and outputs an address mismatch signal when they do not match; a write timing control unit that outputs a write instruction and an address addition instruction; an address control unit that outputs an address incremented by 1 based on the address addition instruction; and a storage section for storing information.
Ｃ実施例〕
次に２本発明について図面を参照して説明する。第１図
は本発明の一実施例のブロック図である。C Embodiment] Next, two embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.
本実施例の診断装置はマイクロプログラムエ００が実行
するマイクロ命令実行アドレス１．０１を一時記憶する
アドレスラッチ３１ｏと、Ｃ３（Ｃ。The diagnostic device of this embodiment includes an address latch 31o that temporarily stores the microinstruction execution address 1.01 executed by the microprogram E00, and C3 (C.
ｎｔｒｏｌ Ｓｔｒａｇｅ ：制御記憶部）２００から
出力され現在実行中のマイクロ命令２０１より１ステッ
プ前に実行されアドレスラッチ３１０が記憶の前実行ア
ドレス３１１に１加算した予測アドレス３２１を出力す
る加算器３２０と、マイクロ命令実行アドレス１０１と
予測アドレス３２１とを比較し不一致のときアドレス不
一致信号３３１を出方する比較器３３０と、アドレス不
一致信号３３１によりライト指示３４１とアドレス加算
指示３４２とを出力すライトタイミング制御部３４０と
、アドレス加算指示３４２により１加算したアドレス３
５１を出力するアドレス制御部３５０と、ライト指示３
４１とアドレス３５１とにより示される番地に前実行ア
ドレス３１１を記憶する記憶部３６０とを有して構成さ
れる。an adder 320 that outputs a predicted address 321 that is output from the control storage unit (control storage unit) 200, is executed one step before the currently executed microinstruction 201, and is obtained by adding 1 to the previously executed address 311 stored by the address latch 310; A comparator 330 that compares the microinstruction execution address 101 and the predicted address 321 and outputs an address mismatch signal 331 when they do not match, and a write timing control section that outputs a write instruction 341 and an address addition instruction 342 based on the address mismatch signal 331. 340 and address 3 added by 1 by address addition instruction 342
Address control unit 350 that outputs 51 and write instruction 3
41 and a storage section 360 that stores the previously executed address 311 at the address indicated by the address 351.
次に動作について説明する。Next, the operation will be explained.
マイクロプロセッサ１００がマイクロ命令実行アドレス
１０１をＣ３２００に与えると、Ｃ８２００は記憶して
いるマイクロ命令２０１を出力する。このときマイクロ
命令実行アドレス１０１はアドレスラッチ３１０に一時
記憶される。アドレスラッチ３１０に記憶され、現在実
行中のマイクロ命令より１ステップ前に実行された命令
のマイクロ命令アドレスである前実行アドレス３１１は
、加算器３２０に入力されて、１加算され、現在実行中
のマイクロ命令アドレスの予測である予測アドレス３２
１が出力される。When the microprocessor 100 gives the microinstruction execution address 101 to the C3200, the C8200 outputs the stored microinstruction 201. At this time, the microinstruction execution address 101 is temporarily stored in the address latch 310. The previous execution address 311, which is stored in the address latch 310 and is the microinstruction address of the instruction executed one step before the currently executing microinstruction, is input to the adder 320 and incremented by 1. Predicted address 32, which is a prediction of the microinstruction address
1 is output.
比較器３３０は、予測アドレス３２１とマイクロ命令実
行アドレス１０１とを比較し不一致である場合にはアド
レス不一致信号３３１をライトタイミング制御部３４０
に与える。アドレスの不連続性が発生したことがアドレ
ス不一致信号３３１によってライトタイミング制御部３
４０に伝えられると、ライトタイミング制御部３４０は
、アドレスの不連続を生じた命令の実行アドレスである
前実行アドレス３１１の記憶及び、引続き実行されるマ
イクロ命令である現在実行中の命令のマイクロ命令実行
アドレス］０１とをアドレスラッチ３１０に一時記憶し
た後、次のクロックサイクルで記憶することを、ライト
指示３４１によって記憶部３６０へ指示する。The comparator 330 compares the predicted address 321 and the microinstruction execution address 101, and if they do not match, sends the address mismatch signal 331 to the write timing control unit 340.
give to The address mismatch signal 331 indicates that address discontinuity has occurred in the write timing control unit 3.
40, the write timing control unit 340 stores the previous execution address 311, which is the execution address of the instruction that caused the address discontinuity, and stores the microinstruction of the currently executed instruction, which is the microinstruction that will be executed subsequently. After temporarily storing the execution address]01 in the address latch 310, the write instruction 341 instructs the storage unit 360 to store it in the next clock cycle.
記憶部３６０は、ライト指示３４１が与えられると前実
行アドレス３１１をアドレス制御部３５０から与えられ
るアドレス３５１で示される番地へ記憶する。アドレス
制御部３５０は記憶部３６０へ与えるアドレス３５１に
、ライトタイミング制御部３４０からのアドレス加算指
示３４２によって、１を加算する。このようにして、マ
イクロプロセッサの命令実行アドレスを、アドレスが連
続的に遷移しなかった場合、すなわちブランチサブルー
チンコール・リターン等の命令が実行された場合、その
命令の実行アドレス及び、その命令が実行された結果次
に実行されるべき命令の実行アドレスにのみ限定して（
例えばブランチ命令が実行された場合、ブランチ命令自
身の存在するアドレス及び、ブランチ先のアドレス）記
憶する。When the storage unit 360 is given the write instruction 341, it stores the previous execution address 311 at the address indicated by the address 351 given from the address control unit 350. Address control section 350 adds 1 to address 351 given to storage section 360 in response to address addition instruction 342 from write timing control section 340 . In this way, if the address does not change continuously in the microprocessor, that is, if an instruction such as a branch subroutine call or return is executed, the execution address of the instruction and the execution address of that instruction can be changed. limited to the execution address of the next instruction to be executed as a result of (
For example, when a branch instruction is executed, the address where the branch instruction itself exists and the address of the branch destination are stored.
以上説明したように本発明は、マイクロプロセッサの命
令実行アドレスが連続的に遷移しなかった場合、その命
令の実行アドレス及び次の命令の実行アドレスにのみ限
定して記憶することにより、マイクロプログラムの実行
結果のトレース情報を効率よく記憶することができると
いう効果がある。As explained above, when the instruction execution address of a microprocessor does not change continuously, the present invention stores only the execution address of that instruction and the execution address of the next instruction. This has the effect that trace information of execution results can be stored efficiently.
第１図は本発明の一実施例のブロック図である。
１００・・・マイクロプロセッサ、１０１・・・マイク
ロ命令実行アドレス、２００・・・Ｃ８，２０１・・マ
イクロ命令、３００・・・診断装置、３１０・・・アド
レスラッチ、３１１・・・前実行アドレス、３２０・・
・加算器、３２１・・・予測アドレス、３３０・比較器
、３３１・・・アドレス不一致信号、３４０・・ライト
タイミング制御部、３４１・・・ライト指示、３４２・
・・アドレス加算指示、３５０・・・アドレス制御部、
３５１・・・アドレス、３６０・・・記憶部。FIG. 1 is a block diagram of one embodiment of the present invention. 100...Microprocessor, 101...Microinstruction execution address, 200...C8, 201...Microinstruction, 300...Diagnostic device, 310...Address latch, 311...Previous execution address, 320...
Adder, 321... Predicted address, 330 Comparator, 331... Address mismatch signal, 340... Write timing control section, 341... Write instruction, 342...
...Address addition instruction, 350...Address control section,
351...Address, 360...Storage unit.
Claims (1)
スを一時記憶するアドレスラッチと、制御記憶部から出
力され現在実行中のマイクロ命令より１ステップ前に実
行され前記アドレスラッチが記憶の前実行アドレスに１
加算した予測アドレスを出力する加算器と、前記マイク
ロ命令実行アドレスと前記予測アドレスとを比較し不一
致のときアドレス不一致信号を出力する比較器と、前記
アドレス不一致信号によりライト指示とアドレス加算指
示とを出力するライトタイミング制御部と、前記アドレ
ス加算指示により１加算したアドレスを出力するアドレ
ス制御部と、前記ライト指示と前記アドレスとにより示
される番地に前記前実行アドレスを記憶する記憶部とを
有することを特徴とする情報処理装置の診断方式。There is an address latch that temporarily stores the execution address of a microinstruction executed by the microprocessor, and an address latch that temporarily stores the execution address of a microinstruction that is output from the control storage unit and is executed one step before the currently executed microinstruction.
an adder that outputs the added predicted address, a comparator that compares the microinstruction execution address and the predicted address and outputs an address mismatch signal when they do not match, and a write instruction and an address addition instruction based on the address mismatch signal. A write timing control unit that outputs an output, an address control unit that outputs an address incremented by 1 based on the address addition instruction, and a storage unit that stores the previously executed address at an address indicated by the write instruction and the address. A diagnostic method for an information processing device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2264143A JPH04140851A (en) | 1990-10-02 | 1990-10-02 | Diagnostic system for information processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2264143A JPH04140851A (en) | 1990-10-02 | 1990-10-02 | Diagnostic system for information processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04140851A true JPH04140851A (en) | 1992-05-14 |
Family
ID=17399060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2264143A Pending JPH04140851A (en) | 1990-10-02 | 1990-10-02 | Diagnostic system for information processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04140851A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07200348A (en) * | 1993-11-23 | 1995-08-04 | Rockwell Internatl Corp | Method and apparatus for compression of program address dataand apparatus for quickening of debugging processing of program |
| JPH08161196A (en) * | 1994-12-09 | 1996-06-21 | Nec Corp | Instruction tracing device |
-
1990
- 1990-10-02 JP JP2264143A patent/JPH04140851A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07200348A (en) * | 1993-11-23 | 1995-08-04 | Rockwell Internatl Corp | Method and apparatus for compression of program address dataand apparatus for quickening of debugging processing of program |
| JPH08161196A (en) * | 1994-12-09 | 1996-06-21 | Nec Corp | Instruction tracing device |
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