JPH04140852A - Diagnostic system for information processor - Google Patents
Diagnostic system for information processorInfo
- Publication number
- JPH04140852A JPH04140852A JP2264144A JP26414490A JPH04140852A JP H04140852 A JPH04140852 A JP H04140852A JP 2264144 A JP2264144 A JP 2264144A JP 26414490 A JP26414490 A JP 26414490A JP H04140852 A JPH04140852 A JP H04140852A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- address
- execution
- storage
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims description 6
- 238000002405 diagnostic procedure Methods 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 4
- 238000003745 diagnosis Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は情報処理装置の診断方式に関し、特にマイクロ
プロセッサが実行した命令実行アドレスをトレースする
情報処理装置の診断方式に間する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a diagnostic method for an information processing device, and particularly to a diagnostic method for an information processing device that traces the execution address of an instruction executed by a microprocessor.
従来の情報処理装置の診断方式において、マイクロプロ
セッサがマイクに命令実行アドレスを制御記憶部に出力
し、制御記憶部からのマイクロ命令をマイクロプロセッ
サが実行し、マイクロプロセッサからの命令実行アドレ
スを記憶手段ですべて記憶する。In a conventional diagnosis method for an information processing device, a microprocessor outputs an instruction execution address to a control storage unit through a microphone, the microprocessor executes a microinstruction from the control storage unit, and the instruction execution address from the microprocessor is stored in a storage unit. Memorize everything.
上述した従来の情報処理装置の診断方式では、記憶手段
の記憶容量の制限により、記憶できる範囲が直前に実行
されたマイクロプログラムアドレスの少量に限られてし
まい、また、マイクロプログラムの処理によっては、命
令の実行アドレスがループするために、必要とするマイ
クロプログラムアドレスの記憶ができないことがあり、
マイクロブログラムのデバッグや障害解析等に十分な効
果を発揮できないという欠点がある。In the above-mentioned conventional diagnostic method for information processing devices, due to the limited storage capacity of the storage means, the range that can be stored is limited to a small number of microprogram addresses that were executed immediately before, and depending on the processing of the microprogram, Because the instruction execution address loops, it may not be possible to store the required microprogram address.
The drawback is that it cannot be sufficiently effective for debugging microprograms, analyzing failures, etc.
本発明の情報処理装置の診断方式は、マイクロプロセッ
サが実行する命令をデコードし、ジャンプ命令とサブル
ーチンコール命令とリターン命令とのアドレス制御命令
を検出し出力する検出手段と、前記アドレス制御命令に
よりマイクロプログラム実行アドレスの記憶タイミング
が制御される記憶指示信号を出力する制御手段と、前記
記憶指示信号により前記マイクロプロセッサのマイクロ
命令実行アドレスを記憶する記憶手段と、この記憶手段
に与える記憶番地を前記制御手段からの増加指示により
増加させるアドレス制御手段とを有する。A diagnostic method for an information processing device according to the present invention includes a detection means for decoding an instruction executed by a microprocessor, detecting and outputting address control instructions such as a jump instruction, a subroutine call instruction, and a return instruction; a control means for outputting a storage instruction signal for controlling the storage timing of a program execution address; a storage means for storing a microinstruction execution address of the microprocessor according to the storage instruction signal; and address control means for increasing the address according to an increase instruction from the means.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のプロ、ツク図であり、マイ
クロ命令セ’７す１００と、ＣＳ （ＣｏｎｔｒｏｌＳ
ｔｒａｇ：制御記憶装置ｉり２００と、診断装置３００
とから構成されている。FIG. 1 is a block diagram of one embodiment of the present invention, including a microinstruction set 100 and a CS (ControlS).
trag: control storage device 200 and diagnostic device 300
It is composed of.
診断装置３００は、命令デコード部３１０と、ライトタ
イミング制御部３２０と、アドレス制御部３３０と、記
憶部３４０とから構成されている。The diagnostic device 300 includes an instruction decoding section 310, a write timing control section 320, an address control section 330, and a storage section 340.
マイクロプロセッサ１００がマイクロ命令実行アドレス
１０１をＣ８２００に与えると、Ｃ８２００は記憶して
いるマイクロ命令２０１を出力する。このとき出力され
たマイクロ命令２０］は命令デコード部３］０に入力さ
れ、ジャンプ命令とサブルーチンコール命令とリターン
命令とのアドレス制御命令が命令デコード部３１０によ
って検出される。アドレス制御命令が検出されたことが
アドレス制御命令検出信号３１１によってライトタイミ
ング制御部３２０に伝えられると、ライトタイミング制
御部３２０はアドレス制御命令の実行されたマイクロ命
令実行アト１／ス１０１及び弓続き実行されるマイクロ
命令のマイクロ命令実行アドレス１０１を記憶すること
をライト指示３２１によって記憶部３４０へ指示する。When the microprocessor 100 gives the microinstruction execution address 101 to the C8200, the C8200 outputs the stored microinstruction 201. The microinstruction 20] outputted at this time is input to the instruction decoding unit 3]0, and the address control instructions of the jump instruction, subroutine call instruction, and return instruction are detected by the instruction decoding unit 310. When the write timing control section 320 is informed that the address control instruction has been detected by the address control instruction detection signal 311, the write timing control section 320 detects the microinstruction execution address 1/s 101 where the address control instruction was executed and the continuation A write instruction 321 instructs the storage unit 340 to store the microinstruction execution address 101 of the microinstruction to be executed.
記憶部３４０は、ライト指示３２】−が与えられるとマ
イクロ命令実行アドレス１０１をアドレス制御部３３０
から与えられるアドレス３３１て示される番地へ記憶す
る。アドレス制御部３３０は記憶部３４０へ与えるアド
レス３３１に、ライトタイミング制御部３２０からのア
ドレス加算指示３２２によって、１を加算する。このよ
うにして、マイクロプロセッサの命令実行アドレスを、
アドレス制御命令の実行アドレス及び引続き実行される
マイクロ命令の実行アドレスにのみ限定して記憶する。When the storage unit 340 receives a write instruction 32]-, the storage unit 340 transfers the microinstruction execution address 101 to the address control unit 330.
It is stored at the address indicated by the address 331 given from . Address control section 330 adds 1 to address 331 given to storage section 340 in response to address addition instruction 322 from write timing control section 320 . In this way, the instruction execution address of the microprocessor is
Only the execution address of the address control instruction and the execution address of the subsequently executed microinstruction are stored.
以上説明したように本発明は、マイクロ７０セツサの命
令実行アドレスを、アドレス制御命令の実行アドレス及
び引続き実行されるマイクロ命令の実行アドレスにのみ
限定して記憶することにより、マイクロプログラムの実
行結果のトレース情報を効率よく記憶することができる
という効果かある。As explained above, the present invention stores the instruction execution addresses of the micro 70 setter only to the execution addresses of address control instructions and the execution addresses of microinstructions to be executed subsequently, thereby improving the execution results of microprograms. This has the effect of allowing trace information to be stored efficiently.
第】図は本発明の一実施例のブロック図である。
１００・・・マイクロプロセッサ、１０１・・・マイク
ロ命令実行アドレス、２００・・・ＣＳ（記憶制御装置
＞、２０１・・・マイクロ命令、３００・・・診断装置
、３１０・・・命令デコード部、３１ドアドレス制御命
令検出信号、３２０・・ライトタイミング制御部、３２
１・・・ライト指示、３２２・・・アドレス加算指示、
３３０・・・アドレス制御部、３３１・・・アドレス、
３４０・・・記憶部。FIG. 1 is a block diagram of an embodiment of the present invention. 100...Microprocessor, 101...Microinstruction execution address, 200...CS (storage control device>, 201...Microinstruction, 300...Diagnosis device, 310...Instruction decoding unit, 31 address control command detection signal, 320... write timing control section, 32
1...Write instruction, 322...Address addition instruction,
330...address control unit, 331...address,
340...Storage unit.
Claims (1)
ンプ命令とサブルーチンコール命令とリターン命令との
アドレス制御命令を検出し出力する検出手段と、前記ア
ドレス制御命令によりマイクロプログラム実行アドレス
の記憶タイミングが制御される記憶指示信号を出力する
制御手段と、前記記憶指示信号により前記マイクロプロ
セッサのマイクロ命令実行アドレスを記憶する記憶手段
と、この記憶手段に与える記憶番地を前記制御手段から
の増加指示により増加させるアドレス制御手段とを有す
ることを特徴とする情報処理装置の診断方式。a detection means for decoding instructions executed by the microprocessor, detecting and outputting address control instructions such as a jump instruction, a subroutine call instruction, and a return instruction; and a memory for controlling the storage timing of the microprogram execution address by the address control instructions. control means for outputting an instruction signal; storage means for storing a microinstruction execution address of the microprocessor in accordance with the storage instruction signal; and address control means for increasing a storage address given to the storage means in response to an increase instruction from the control means. A diagnostic method for an information processing device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2264144A JPH04140852A (en) | 1990-10-02 | 1990-10-02 | Diagnostic system for information processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2264144A JPH04140852A (en) | 1990-10-02 | 1990-10-02 | Diagnostic system for information processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04140852A true JPH04140852A (en) | 1992-05-14 |
Family
ID=17399074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2264144A Pending JPH04140852A (en) | 1990-10-02 | 1990-10-02 | Diagnostic system for information processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04140852A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07200348A (en) * | 1993-11-23 | 1995-08-04 | Rockwell Internatl Corp | Method and apparatus for compression of program address dataand apparatus for quickening of debugging processing of program |
-
1990
- 1990-10-02 JP JP2264144A patent/JPH04140852A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07200348A (en) * | 1993-11-23 | 1995-08-04 | Rockwell Internatl Corp | Method and apparatus for compression of program address dataand apparatus for quickening of debugging processing of program |
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