JPH01156823A - Microprocessor unit - Google Patents

Abstract

PURPOSE:To easily eliminate a bag if contained in a microprogram by starting the microprogram in the middle of an executing microprogram routine after designating an executing address of the microprogram by a software instruction. CONSTITUTION:An interruption signal 7 is delivered from a microaddress jump control unit 5 and supplied to a microsequencer 3. In this case, the sequencer 3 fetches an address out of a microaddress register 51 to transfer it to a microprogram ROM 1 and at the same time sends an interruption release signal 9 to a microaddress control switch 52 of the unit 5 to release the signal 7. Thus the executing address of the microprogram is designated by a main program stored in a main memory. In such a way, a program is carried out with elimination of the bag of a microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprocessor unit that incorporates a microprogram and that reads and executes instructions from a main memory via an external bus.

(Prior Art) Conventionally, this type of microprocessor unit has a microprogram ROMI storing a microprogram and a bus control unit 2, as shown in FIG.
, a micro-sequencer 3 that reads a main program from a main memory (not shown) via a bus control unit 2 and generates an execution address for the micro-program; and a micro-program ROMI read out using the execution address generated by the micro-sequencer 3. and an execution unit 4 that executes instructions from and accesses an external device (not shown) via the bus control unit 2.

In this microprocessor unit, the microsequencer 3 reads an instruction from a main memory (not shown) via the bus control unit 2 and decodes the instruction, thereby starting execution of the instruction. Subsequently, the microsequencer 3 generates a start address for the microprogram and outputs it to the microprogram ROMI. As a result, a microprogram is output from the microprogram ROMI, taken in by the execution unit 4, and executed. When the execution unit 4 completes its processing, it requests the next data from the microsequencer 3, and thereafter repeats the same operation.

[Problem that the invention seeks to solve]

In conventional dual microprocessor units, the start address of the microprogram to be executed is determined by a software instruction, so if a microprogram with several steps is executed, if there is a bug in the microprogram, the instruction itself becomes unusable,
Another disadvantage is that if a buggy software instruction is to be replaced with another instruction and then executed, a very large number of steps of software instructions must be used.

[Means for solving problems]

The microprocessor unit of the present invention includes a microb storing a microprogram, a program ROM, and a bus control unit.

It fetches an instruction from the main memory via a bus control unit, generates an execution address for a microprogram, and outputs it to the microprogram ROM, and when the instruction is a microaddress instruction that specifies a microprogram to be executed, an interrupt is generated. A micro sequencer that receives a signal, takes in the specified address of the microprogram, and cancels the interrupt signal, and a micro sequencer that receives the microprogram from the microprogram ROM, executes the instructions, and connects an external device via the bus control unit. an execution unit that takes in a specified address via a bus control unit and outputs the address and an interrupt control signal when the instruction decoded by the microsequencer is a navigation microaddress instruction; It consists of a microaddress register that receives and stores the specified address, and a microaddress control switch that receives an interrupt control signal from the execution unit and outputs the interrupt signal to the microsequencer after the microaddress register stores the specified address. and a microaddress jump control unit.

(Function) By the main program stored in the main memory,
Since you can specify the execution address of the microprogram,
The program can be executed while avoiding bugs that occur in the microprogram.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the microprocessor unit of the present invention, and FIG. 2 is a block diagram showing the configuration of the microaddress jump control unit 5 of FIG. 1.

As shown in FIG. 1, this microprocessor is connected to a main memory (not shown) via an external bus 6.
It is composed of a microprogram ROMI, a bus control unit 2, a microsequencer 3, an execution unit 4, and a microaddress jump control unit 5. As shown in FIG. 2, the microaddress jump control unit 5 is composed of a microaddress register 51 and a microaddress control switch 52, and the microaddress register 51 stores the address of the microprogram from the execution unit 4. However, the microaddress control switch 52 outputs an interrupt control signal 8 from the execution unit 4 when the microaddress register 51 stores an address.
is set and outputs an interrupt signal 7 to the microsequencer 3, and after the microsequencer 3 fetches the address from the microaddress register 51 by the interrupt signal 7, an interrupt release signal 9 is sent from the microsequencer 3.
The interrupt signal 7 is reset by this. The micro sequencer 3 takes in instructions from the main memory via the bus control unit 2, generates an execution address for the microprogram, and outputs it to the microprogram ROMI, and the instructions from the main memory specify the microprogram to be executed. When a microaddress instruction is issued, receiving an interrupt signal 7 from the microaddress jump control unit 5,
It takes in the address from the micro address jump control unit 5h1 and further outputs an interrupt release signal -9 to the micro address jump control unit 5. The execution unit 4 receives a microprogram from the microprogram ROMI and executes the instruction, and if the instruction is an instruction indicating the above-mentioned microaddress instruction,
The specified address of the microprogram is taken in via the bus control unit 2 and the address and interrupt control signal 8 are output to the microaddress jump control unit 5.

Next, the operation of this embodiment will be explained.

First, the interrupt signal 7, interrupt control signal 8, and interrupt release signal 9, which are input and output of the microaddress control switch 52 of the microaddress jump control unit 5, are set to the "L" level as initial values. Usually micro sequencer 3
However, if the decoded instruction is the microaddress instruction mentioned above, the microsequencer 3 reads the instruction from the main memory via the bus control unit 2 and decodes the instruction. A program address is generated and transferred to the microprogram ROMI, and an instruction corresponding to the address is extracted and output to the execution unit 4. Upon receiving the instruction, the execution unit 4 controls the bus control unit 2 to fetch the address of the microprogram specified by the microaddress instruction from the main memory via the external bus 6, and sends it to the microaddress jump control unit 2. At the same time, the interrupt control signal 8 is output to the microaddress control switch 52 to generate an interrupt signal 7. In this way, when the interrupt signal 7 is output from the microaddress jump control unit 5 and inputted to the microsequencer 3, the microsequencer 3 takes in the address stored in the microaddress register 51 and starts the microprogram ROMI.
At the same time, the interrupt cancel signal 9 is sent to the micro address control switch 52 of the micro address jump control unit 5 to cancel the interrupt signal 7. Thereafter, the microprogram corresponding to the address is extracted from the microprogram ROMI and sequentially processed by the execution unit 4.

〔Effect of the invention〕

As explained above, in a microprocessor unit having a built-in microprogram, the present invention specifies the execution address of the microprogram using a software instruction and starts the microprogram from the middle of the execution microprogram routine. This has the effect that if there is a bug, it can be easily avoided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the microprocessor unit of the present invention, FIG. 2 is a block diagram showing the configuration of the microaddress jump control circuit 5 of FIG. 1, and FIG. 3 is a block diagram of a conventional microprocessor unit. It is a block diagram showing an example. ! . . . Micro program ROM, 2. Bus control unit, 3. Micro sequencer, 4. Execution unit, 5. Micro address jump control unit, 6.
...External bus, 7...Interrupt signal, 8...Interrupt control signal, 9...Interrupt release signal, 5t-...Micro address register, 52...Micro address control switch.

Claims (1)

[Scope of Claims] A microprocessor unit that incorporates a microprogram and processes instructions by fetching them from a main memory via an external bus, comprising: a microprogram ROM that stores the microprogram; and a bus control unit. and fetching an instruction from the main memory via the bus control unit to generate an execution address for the microprogram and outputting it to the microprogram ROM, and when the instruction is a microaddress instruction specifying a microprogram to be executed, A micro sequencer that receives an interrupt signal, fetches the specified address of the microprogram, and cancels the interrupt signal, and a microsequencer that receives the microprogram from the microprogram ROM and executes its instructions and sends it to the outside via the bus control unit. an execution unit that accesses the device and takes in a specified address via a bus control unit and outputs the address and an interrupt control signal when the instruction decoded by the microsequencer is the microaddress instruction; It consists of a microaddress register that receives and stores an address, and a microaddress control switch that receives an interrupt control signal from the execution unit and outputs the interrupt signal to the microsequencer after the microaddress register stores the specified address. a microprocessor unit having a microaddress jump control unit;