JPH02299029A - Processor - Google Patents

Abstract

PURPOSE:To securely make a debugging interruption request by performing interruption processing for the debugging interruption request by a processor which has a debugging function and interruption processing for other interruption requests other than the debugging interruption request by different methods respectively. CONSTITUTION:When a debugging interruption is initiated during the debugging of a program to be debugged, an interruption control circuit 12 supplies an instruction for the output of the contents of a vector register 13 to an internal data bus 7 to a vector register 13. Consequently, the head address of a debugging interruption handler stored previously in the vector register 13 is outputted to the bus 7. The head address which is outputted to the bus 7 is fetched by a program counter 14 and stored and held. Then the debugging interruption handler is started with the head address stored in the program counter 14 and a debugging program moves to the interruption routine corresponding to the interruption request.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a processor having a debug function,
In particular, it relates to a processor with improved interrupt processing during debugging.

(Prior Art) In recent years, processors with internal debugging functions have been developed for the purpose of increasing the efficiency of development and evaluation.

An example of such a processor is one configured as shown in FIG. 3, for example. FIG. 3 is a diagram showing a schematic configuration for executing interrupt processing in a processor.

In processor 1, when debugging a program to be debugged, a debug interrupt (interrupt during debugging, EIT, ExceptionInterrupt)
rupt trap is especially called debug interrupt.
When an interrupt (distinguished from an interrupt that occurs during normal program execution) occurs, a vector table entry (EI
TVTE) is specified.

The interrupt header table is provided outside the processor 1 and is connected to the external address bus 3 under the control of the memory control circuit 2.
External data bus 4 according to the address given from
and an external memory 5 through which data is input and output. The interrupt vector table is composed of a plurality of vector table entries (Er-rVTE) as shown in FIG. The vector table entry consists of elements for executing an interrupt processing routine, one of which is vPC data. The interrupt header table is allocated on the logical space with respect to the external memory 5, and its first logical address is the EIT provided in the processor 1.
It is stored and held in the vector table base register (EITVB) 6.

Therefore, for example, when each vector table entry has a length of 8 bytes, the logical address of the vector table entry is the sum of the interrupt vector number multiplied by 8 and the value of the vector table register.

That is, the interrupt vector number of the generated interrupt is given to the interrupt control circuit 8 via the internal data bus 7, and the starting logical address of the vector table is given from the pace register 6 to the interrupt control circuit 8 via the internal data bus 7. , the address of the vector table entry corresponding to the generated interrupt request is determined by the υj interrupt control circuit 8 as described above.
determined by The address determined by the interrupt control circuit 8 is given to the external bus control circuit 9 via the internal data bus 7, and from the external bus control circuit 9 to the external memory 5 via the external address bus 3 and the memory control circuit 2. It will be done. As a result, the vector table entry corresponding to the address determined by the interrupt control circuit 8 is read from the external memory 5.

The read vector table entry is applied to the external bus control circuit 9 of the processor 1 via the external data bus 4, and from this external bus control circuit 9 to the internal data bus 7. Among the vector table entries given to the internal data bus 7, VPC data is stored and held in a program counter (PC) 10. As a result, the contents of the program counter 10 are updated.

The vPC data stored in the program counter 10 is
Indicates the start address of the debug interrupt handler for executing debug interrupt requests. therefore,
When the vPC data is stored in the program counter 10, the debug interrupt handler specified by the start address indicated by the VPC data is activated and debug interrupt processing is started. Note that the contents of the interrupt cover table and vector table register 6 can be easily changed by an external program.

In this way, debug interrupt requests that occur during program debugging are processed, and this debug interrupt processing is performed in the same way as the interrupt processing for other interrupts other than debug interrupts.

(Problems to be Solved by the Invention) As described above, in conventional processors equipped with a debug function, debug interrupt processing is performed in the same manner as other interrupt processing. That is, the vector table entry corresponding to the generated interrupt request is read from the external memory, the PC data of this vector table entry is stored in the program counter, and the debug interrupt handler is activated by this VPC data.

On the other hand, the EIT vector table base register (EITV
B) and the contents of the vector table entry can be rewritten by a user program. For this reason, E
When the contents of ITVB are rewritten to change the area of the EIT vector table, the contents of the vector table entry used by debug interrupts may not be moved to the newly changed area. Also, the contents of the vector table used by the debug interrupt may be read. In such a case, even if a debug interrupt occurs during debugging, it will be difficult to return control to the debug program that is being debugged, resulting in a problem that will make it impossible to continue debugging. It turns out.

Therefore, the present invention has been made in view of the above, and its purpose is to be able to reliably process debug interrupt requests during debugging even if the interrupt status changes. An object of the present invention is to provide a processor having a debug function.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention includes a first holding means for storing and holding specification information specifying an interrupt processing routine corresponding to an interrupt request. , in a processor having a debug function that executes an interrupt processing routine specified by the specification information held in the first holding means when an interrupt request occurs, a specification for specifying a debug interrupt processing routine that occurs when debugging a program. It is comprised of a second holding means for storing and holding information, and a control means for causing the first holding means to transfer and hold the designation information held by the second holding means when a debug interrupt request is generated.

(Operation) In the above configuration, when a debug interrupt request occurs, the present invention specifies the debug interrupt processing routine using the specification information held in the dedicated holding means for specifying the debug interrupt processing routine, and It handles interrupt requests.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, and a processor 11 shown in the figure is equipped with a debug function and is connected to an external memory 5. Note that in FIG. 1, the same reference numerals as in FIG. 3 have the same functions, and the explanation thereof will be omitted.

In FIG. 1, a processor 11 includes an interrupt control circuit 1
2. It is mainly composed of a debug interrupt vector register (DBV) 13 and a program counter (PC) 14.

The interrupt control circuit 12 responds to interrupt requests that occur outside of debugging using the interrupt! shown in FIG. II i1
1 circuit 8, the address of the vector table entry of the interrupt vector table is determined from the vector number of the generated interrupt and the contents of the pace register 6. On the other hand, when a debug interrupt occurs, the interrupt control circuit 12 causes the vector register 13 to output the stored contents to the internal data bus 7, and causes the program counter 14 to take in the contents of the vector register 13 output to the internal data bus 7. give instructions.

The K1-inclusive control circuit 12 may be configured to control the above operations using a microprogram, or may be configured as a circuit.

The vector register 13 stores and holds the start address value of a debug interrupt handler for executing a debug interrupt. This address value is set in the vector register 13 in advance before interrupt processing is started, and the set address is output to the internal data bus 7 by a command from the interrupt control circuit 12.

When an interrupt request occurs other than during debugging, the program counter (PC>14) is the VPC of the vector entry read from the external memory 5, similar to PC3 shown in FIG.
Data is stored and retained.

On the other hand, when a debug interrupt request occurs, the program counter 14 transfers the address given from the vector register 13 to the internal data bus 7 to the interrupt control circuit 12.
Capture and store and hold under the control of.

As explained above, one embodiment of the present invention is constructed, and the operation of this embodiment will now be explained with reference to FIG. 2.

When a debug interrupt occurs during debugging of a program to be debugged, a command to output the contents of the vector register 13 to the internal data bus 7 is given to the vector register 13 from the interrupt control circuit 12. As a result, the start address of the debug interrupt handler previously stored in the vector register 13 is output to the internal data bus 7.

The start address output to the internal data bus 7 is the program counter 1 controlled by the training control circuit 12.
4 and stored and held.

Then, the debug interrupt handler is activated by the start address stored in the program counter 14, and the debug program shifts to an interrupt processing routine corresponding to the interrupt request.

In this way, in this embodiment, the debug interrupt handler is specified separately from other interrupt processes, and the debug interrupt handler is specified according to the contents of the vector register 13. Even if the VPC data of VPC changes, it will not affect the debug interrupt processing in any way. Therefore, even if a debugging interrupt occurs, it is possible to continue executing the debugging work up to that point.

Therefore, it becomes possible for the user to handle interrupts other than debugging interrupts, and the user can perform debugging operations reliably and smoothly.

Furthermore, by specifying the start address of the debug interrupt handler using the value stored in the register, it becomes possible to place the debug program at an arbitrary address, increasing the versatility of the system as a whole.

Note that the present invention is not limited to the above-described embodiment, and for example, the start address of the debug interrupt handler may be stored and held in a register provided outside the processor 11. Alternatively, the information may be stored at a predetermined address in an external memory.

[Effects of the Invention] As explained above, according to the present invention, the interrupt processing of a debug interrupt request in a processor having a debug function and the interrupt processing of other interrupt requests other than the debug interrupt request are performed by separate methods. So even if the state of the interrupt changes,
It becomes possible to reliably and easily execute a debug interrupt request that occurs during debug work without changing the debug program.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the configuration shown in FIG. 1, FIG. 3 is a configuration block diagram including a conventional processor having a debug function, and FIG. The figure is an explanatory diagram of the operation of the configuration shown in FIG. 3. 2... Memory control circuit 5... External memory 6... Lid to EIT Table base register 9...
External bus control circuit 11...Processor 12...Interrupt control circuit 13...Debug interrupt vector register 14...Program counter

Claims (1)

[Scope of Claims] The first holding means stores and holds specification information specifying an interrupt processing routine corresponding to an interrupt request, and when an interrupt request occurs, the specification information held in the first holding means A processor having a debug function that executes a specified interrupt processing routine, the second storage means storing and holding specification information specifying a debug interrupt processing routine that occurs when debugging a program; A processor comprising: control means for transferring and holding specification information held by the second holding means to the first holding means.