JPS6029846A - Execution state control system of information processor - Google Patents

Abstract

PURPOSE:To fetch an operand stored in a storage part as a substitute for an instruction address when the execution of a program at an interruption destination is restarted, by storing the address of an instruction value at the interruption destination in the storage part as the operand when the execution state of an interruption program is set. CONSTITUTION:A program to be debugged is executed to fetch a debug instruction at a debug address position and execute it, and an interruption is caused by a debug event to exchange a PSW (program status word), thereby setting an original PSW in a specific address of a main memory 18. A control part 13 fetches an instruction in the main memory 18 on the basis of the PSW fetch type instruction. An arithmetic part 13 judges whether the fetched instruction is a PSW load instruction or not, nd when so, the corresponding microprogram is executed by the microprogram control part in the control part 13. Lastly, the execution state of the arithmetic part 11 of a processor is so set that an instruction is already set, and the microprogram completes the processing.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] This invention is directed to controlling the execution of a program using a stored program system, and controlling the processing state of the program.
The present invention relates to an execution state control method in an information processing apparatus that employs a so-called PSW loading method that can be set using a status word (hereinafter referred to as PSW).

[Prior art and its problems]

Generally, the Psw load method is a method in which the information processing device controls the execution state of a program by using an instruction to return program execution control to the original interrupt destination when the information processing device finishes processing corresponding to the generated interrupt. It is. Conventionally, this method uses two
8w load instruction, an instruction that the information processing device judges and executes (or is realized as a machine instruction), determines the data specified as the operand of this instruction as a switching PSW, and uses this to control the execution state of the program. For example, the so-called 2 of Eva, Stenix register, and program counter
It is set as is in the 8w register.

However, as shown in FIG. 1(a), when debugging a program, a debug instruction 2 that generates an interrupt due to a debug event is sent to an arbitrary debug address (interruption point) 3 on the program to be debugged. When performing debugging processing that dynamically sets the debugging program 5, the execution state of the debugged program 1 that was interrupted by the debugging instruction 2 is checked in the debugging program 5 that is executed after the interrupt. . When implementing a debugging method that performs this as debugging processing 6 corresponding to interrupts, the conventional PSW load instruction cannot be used as is when continuing debugging, and the following There is a problem in that one of these processes must be performed.

(1) As shown in FIG. 1(b), the previous instruction (instruction a here) that was replaced with the debugging instruction, this instruction a, is subjected to alternative execution processing 7 when resuming execution of the debugged program. , then execution processing 8 must be performed to execute the PSW load instruction (see debug processing program 5). However, in this case, the length of instruction a, the type of instruction, the method of extracting operands, etc. vary, so alternative execution is complicated and difficult.

(2) Another restart method from (1) above is to return the previous instruction a, which was replaced with the debug instruction, to the position indicated by the debug address again, and set the program counter value of the PSW value that is the operand of the PSW load instruction. Operate and PS
Execute the W load command.

However, in this case, a debug instruction once set is canceled each time it is executed, so if the same part of the program is repeatedly executed, it is necessary to set the debug instruction each time.

[Purpose of the invention]

The present invention has been made in view of the problems of the prior art, and its purpose is to resume execution of an interrupted program after processing an interrupt without performing any pre-processing. The present invention provides an execution state control method for an information processing device that makes it possible to perform the following operations.

[Key points of the invention]

In an information processing device, when loading a program status word that sets the execution state of an interrupt program, the instruction address at the interrupt destination and the address of the program status word value are stored as □ operands in a storage unit. The operand stored in the storage unit is read in place of the instruction address in the program status word when the execution of the interrupt destination program is resumed.

[Embodiments of the invention]

The present invention will be explained below based on the drawings.

FIG. 2 is an explanatory diagram showing an example of how a PSW load instruction is used during debugging in an embodiment of the present invention, and FIG.
FIG. 1 is a block diagram showing an information processing device to which the present invention is applied.

In FIG. 3, 10 is an external register including a program counter, 11 is an arithmetic unit, 12 is a shifter, 13 is a control unit including a microprogram control unit, 14 is a control memory including an instruction prefetch buffer memory 15,
16 is an internal register consisting of a status register, etc.;
7 is a memory access control section, 18 is a main memory, and 19 is an option calculation section. Here, control memory 1
4 stores a microprogram, and the main memory 18 stores a program to be debugged.

Next, to explain the operation, first, as shown in FIG. Replace with This replaced instruction a is stored at a predetermined address in the main memory 18 separate from the program to be debugged.

Next, the program to be debugged is executed, a debug instruction is fetched at the debug address location, and when this is executed, an interrupt is generated due to a debug event, the PSW is exchanged, and the original PSW is stored in the predetermined main memory. The address is set to 18. Then, as interrupt processing, the PSW of the debug event is read from a predetermined address, and control is transferred to the debug processing program 23.

This debugging processing program 23 performs necessary debugging processing 24 (for example, processing such as checking registers at the time of suspension, referencing/changing the related main memory 18, etc.). Then, in order to resume execution of the program to be debugged at the end of the debugging process, the psw load instruction 25 of the instruction capture type that implements the method of the present invention is executed. This P
As shown in Figure 2 (C), the SW load instruction has as operands the storage address of the PSW value before the interrupt occurred and the storage address of the previous instruction a replaced by the debug instruction, and these are specified. and execute it.

Based on this psw import type command, the control unit 13:
The instruction on the main memory 18 corresponding to the address indicated by the program counter, which is one of the external registers 10, is fetched.

This fetched instruction is decoded by the control unit 13 and sent to the calculation unit 11, which performs a logical operation to determine whether or not it is a PSW load instruction.If it is a PSW load instruction, The microprogram corresponding to this instruction is the microprogram control section in the control section 13,
This is executed while referring to the control memory 14.

This corresponding microprogram reads the instruction a from the main memory 18 according to the storage address of the instruction a, which is the first operand, and sets it in the instruction prefetch buffer 15 in the control memory 14.

Next, this PSW value is retrieved from the main memory 18 according to the address value of the PSW value, which is the second operand, and the status value of the PSW value is set in the status register, which is one of the internal registers 16. The address value is manipulated (eg, decremented) and set in a program counter, which is one of the external registers 10.

Finally, the microprogram sets the execution state of the arithmetic unit 11 of the processing device to a state in which the instructions have already been taken in, and ends the processing.

Next, the processing unit 13 shifts to processing the next instruction from the point at which it completes fetching the instruction.

In this way, execution of the program to be debugged can be resumed as if instruction a existed at the address replaced by the debug instruction.

Therefore, when applied to a debugging tool that debugs a program while dynamically inserting debug instructions to any debug address of the debugged program, it makes the procedure for resuming execution of the debugged program easier. be able to. In this case, the debugging tool may be an interactive program debugging tool or an online software debugging tool, but these tools can be created very easily.

Note that the above embodiment shows one embodiment of the present invention, and in addition to the above embodiment, there is a restriction that the method of the present invention is used for purposes other than debugging in an information processing device. In order to do so, it is also possible to provide the following additional functions.

That is, by referring to the address value of the PSW value of the instruction capture type, the function number is performed only when the instruction at the previous address value indicated by the address value is a debug instruction, and in other cases, It is also possible to generate an interrupt for another command event of the information processing device. Further, the debug instruction and the instruction-capturing psw load instruction may be enabled only when the execution mode of the information processing device is the debug mode.

On the contrary, in the above embodiment, the case where debugging processing is performed as an interrupt processing has been described, but the invention is not limited to this, and the present invention can also be applied to cases where other interrupt processing is performed. Of course you can get it.

〔Effect of the invention〕

As described above, according to the present invention, in an information processing device, when loading a program status word that sets the execution state of an interrupt program, the instruction address of the interrupt destination and the address of the program status word value are The operand is stored as an operand in the storage section, and when execution of the program at the interrupt destination is resumed, the operand a written in the storage section is read in place of the instruction address in the program status word. For this reason, when performing interrupt processing while dynamically inserting an interrupt instruction at an arbitrary interrupt address (interruption point) in a program, which has traditionally been complicated and cumbersome, the procedure for resuming program execution has been improved. It can be done easily.

Further, the interrupt command inserted into the program indicated by the interrupt address can be left as is until the time the user intends, and there is no need to reset it.

Furthermore, even if an interrupt instruction has not been inserted in advance in an executable program, it is possible to dynamically determine and insert an interrupt address. No need to reassemble.

In addition, instructions on a program that have been replaced by interrupt instructions can be managed using replacement addresses, so even if multiple interrupt addresses are stored at the same time, interrupt processing can be performed. be.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an example of how a PSW load instruction is used during debugging according to a conventional method, and FIG. 2 is an explanatory diagram showing an example of how a psW load instruction is used during debugging according to an embodiment of the present invention. , FIG. 3 is a block diagram showing an example of an information processing device that can be applied to the method of this invention. 10: External register, 11: Arithmetic unit, 13: Control unit, 14: Control memory, 15: Instruction prefetch buffer ,
16...Internal register, 17...Memory access control unit, 18...Main memory. Patent Applicant Fuji Electric Manufacturing Co., Ltd. Fuji Facom Control Co., Ltd. Agent Patent Attorney Tetsuya Mori Agent Patent Attorney Internal Review Agent Patent Attorney Shimizu Authorized Agent Patent Attorney Submission Faith

Claims (1)

[Claims] In an information processing device, when loading a program status word that sets the execution state of an interrupt program, the replacement source instruction address at the interrupt destination and the address of the program status word value are stored in the storage unit as operands. 1. An execution state control method for an information processing apparatus, characterized in that an operand stored in the storage section is fetched in place of an instruction address in a program status word of an interrupt destination when program execution is resumed.