JPS63289653A - In-circuit emitter - Google Patents

Abstract

PURPOSE:To execute program debugging including interruption processing under a condition similar to that of a user system by reading out an interruption vector based on an interruption signal and executing interruption processing in a jumped address. CONSTITUTION:When an interruption request is generated in an interruption timing generator during the fetching and execution of a program in an internal memory 3 from/by an emulation processor 4, an interruption controller 12 outputs an interruption signal, the inverse of INT, to the processor through an AND gate 23. At the time of receiving the interruption, the processor 4 activates a signal, the inverse of INTA, and saves a current program counter or the like. Then, the processor 4 reads out an interruption vector from an interruption vector storing part 13, outputs a jumped address signal in accordance with the interruption vector and fetches the interruption processing program from the internal memory 3 to execute it.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an in-circuit emulator, and more particularly to an in-circuit emulator that can debug a user program without connecting a user system.

[Conventional technology]

Conventionally, when debugging a program developed by a user without connecting the user system, this type of in-circuit emulator has been used to handle interrupt processing and hold processing even if the user system is configured to use interrupt requests and hold requests. To run the program as a continuous program, or to debug with interrupt requests and hold requests, use the break function. This was configured to be done by inputting a command.

[Problem that the invention seeks to solve]

The conventional in-circuit emulator described above is configured to use a break function to reflect the effects of interrupt requests and hold requests when debugging a user program without connecting the user system. When this function is used, the execution of the user program is stopped, break processing is performed including processing of interrupt requests, etc., and then the execution of the user program is started again. This time is converted into the original interrupt processing time or hold period. The disadvantage is that it is orders of magnitude longer (usually on the order of seconds).

Furthermore, in an emulation microprocessor equipped with a memory management mechanism and cache function, the memory space changes when a break occurs, so the contents of the memory management mechanism and cache memory are cleared, and the execution conditions are significantly different, causing timing problems. The drawback is that important programs cannot be debugged sufficiently.

Furthermore, even if an attempt is made to debug a program that combines a main routine and an interrupt processing routine, the interrupt processing routine cannot be activated, so there is a drawback that it is impossible to debug a program that is a combination of these routines.

SUMMARY OF THE INVENTION An object of the present invention is to provide an in-circuit emulator that allows debugging of a program that reflects interrupt processing and the like in a short time under conditions similar to those of the user system.

[Means for solving problems]

The in-circuit emulator of the present invention includes an interrupt signal generation section that generates an interrupt signal at a predetermined timing based on set conditions, and either an interrupt signal from the interrupt signal generation section or an interrupt signal from the user system side. an interrupt control unit that selects an interrupt vector; an interrupt vector storage unit that outputs a preset interrupt vector based on the interrupt signal; and an interrupt vector storage unit that stores at least a program to be debugged and an interrupt processing program at predetermined addresses, respectively, and outputs a preset interrupt vector based on the interrupt signal. An internal memory for reading the program at these addresses, and an address signal for the address where the debugged program (lag program) is stored are sequentially output, and the program to be debugged is read from the internal memory and executed, and the interrupt signal is When input, the interrupt vector is read and the address signal corresponding to this interrupt vector is output, and the interrupt processing program is read from the internal memory and executed. When the execution of this interrupt processing program is finished, the program to be debugged is restarted. and an emulation processor that returns to execution.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The interrupt signal generator 1 includes an interrupt timing generator 11 and an interrupt controller 12, and generates an interrupt signal at a predetermined timing based on condition setting data DTs from the data bus.

The interrupt controller 12 is also provided with an interrupt vector storage section that stores interrupt vectors.

The interrupt control unit 2 includes an interrupt prohibition switch 21, a gate 22, and an AND gate 23, and selects either the interrupt signal from the interrupt signal generator 1 or the interrupt signal from the user system 10.

The internal memory 3 stores at least a user-developed program to be debugged and an interrupt processing program at predetermined addresses, and reads and outputs the program at a predetermined address in accordance with an address signal.

Normally, the emulation processor 4 sequentially outputs address signals of addresses where the program to be debugged is stored, reads and executes the program to be depacked from the internal memory 3, and when an interrupt signal INT is input, it outputs an interrupt response signal INTA. The interrupt vector is read from the interrupt vector storage section 13, the address signal corresponding to this interrupt vector is output, and the interrupt processing program is read from the internal memory 3 and executed. When the execution of the interrupt processing program is finished, the program to be debugged is returned. Return to program execution.

The distributor 5 outputs the interrupt response signal INTA to the buffer circuit 8 and the interrupt controller 12 to enable transmission of the interrupt vector when the user system 10 is not connected, and outputs the interrupt response signal INTA when the user system 10 is connected. Output INTA to the mapping circuit 6.

The mapping circuit 6 includes internal memory and memory for each address.
User memory selection information is stored, and the buffer circuit 7 or 9 is activated to select either the internal memory 3 or the user memory of the user system 10 according to an address signal. However, when the interrupt response signal INTA is input from the distributor 5, the buffer circuit 9 is forced to
Activate.

Next, the operation of this embodiment will be explained.

Normally, when designing, developing, and debugging the hardware and software of a user system, the hardware is often incomplete, and it is often necessary to debug only the software.

In this case, the user system is not connected to the in-circuit emulator, but the program to be debugged is loaded into the internal memory of the in-circuit emulator and debugged.

The object of the present invention is to provide a debug function in this state, and the following explanation is an explanation of the operation in this state.

Since the user system 10 is not connected, the interrupt disable switch 21 outputs a high level and the user system 10
Disable the side interrupt signal.

The mapping circuit 6 is set to access the internal memory 3 for all address spaces used. Distributor 5
is set to output the interrupt response signal INTA output from the emulation processor 4 to the buffer circuit 8 and the interrupt controller 12.

When you run this in-circuit emulator with such settings, the emulation processor usually
The address signal AD is output according to the contents of the program counter, and the program to be debugged is sequentially fetched from the internal memory 3 and executed.

When the user performs debugging including interrupt processing, etc., set the conditions for each part as follows.

First, condition setting data DTs is input from a control CPU (not shown) to the interrupt timing generator 11 via a data bus, and settings are made to generate an interrupt signal at a predetermined period. Furthermore, an interrupt vector is set in the interrupt vector storage section 13 of the interrupt controller 12.

When the emulation processor 4 is operated after completing this setting, the emulation processor 4 sequentially fetches the programs in the internal memory 3 and proceeds with execution.

When an interrupt request is generated by the interrupt timing generator 11, the interrupt controller 12 outputs an interrupt signal INT to the emulation processor 4 via the AND gate 23.

When the emulation processor 4 is enabled to accept interrupts and accepts the interrupt, it activates the interrupt response signal INTA to process the interrupt, saves the current program counter contents, etc., and then interrupts the interrupt controller 12. An interrupt vector is read from the interrupt vector storage section 13 of the interrupt vector, a jump destination address signal is output according to the interrupt vector, and an interrupt processing program is fetched from the internal memory 3 and executed.

After the execution of this interrupt processing program is completed, execution of the original program to be debugged is resumed. Interrupt processing time can be set in real time.

By repeating this operation, it is possible to execute a program in which an interrupt processing program is inserted into the debugged program at any time, and it is possible to create an operating environment similar to the program running on the user system.

In addition, if the user system is configured to operate serial I10 by interrupt, serial I1 of the interrupt processing
By changing the 0-access program and data to be stored and accessed in the internal memory 3, debugging, etc., including processing when a certain data string is input from the serial I10, becomes possible only within the in-circuit emulator. .

FIG. 2 is a block diagram showing a second embodiment of the invention.

This second embodiment differs from the first embodiment in that
An embodiment of the interrupt signal emulation processor 4
In contrast, in the second embodiment, the interrupt response signal is input to the INT terminal of the interrupt controller 12, the interrupt response signal is output from the INTA terminal, and the interrupt vector is read from the interrupt vector storage section 13 in the interrupt controller 12. The non-maskable interrupt pin NMI of the emulation processor 4a
(hereinafter referred to as the NMI terminal), therefore, the interrupt response signal is not output and the process immediately shifts to interrupt processing.
It is at the point set at a.

Since the NMI terminal input of the interrupt signal immediately transitions to interrupt processing regardless of the state of the emulation processor 4a, when using a hold request (a request to temporarily stop CPU operation) in the user system, it is possible to use a hold period similar to the hold period. If an NMI processing program with time is prepared, the program to be debugged can be debugged at the same timing as the user system without being connected to the user system.

Of course, if the user system uses the NMI terminal, debugging including the NMI processing program can be performed without connecting to the user system.

〔Effect of the invention〕

As explained above, the present invention provides an interrupt signal generation section that generates an interrupt signal at a predetermined timing and an interrupt vector storage section that sets the address of the jump destination, and reads out the interrupt vector according to the interrupt signal and reads the interrupt vector as the jump destination. By configuring the program to execute the interrupt processing program at the address of , the program to be debugged, including interrupt processing, can be debugged in a short time in an environment close to that of the user system, even without connecting the user system. There is an effect that can be achieved.

However, since factors that affect execution time, such as hold requests, can be simulated, it is possible to debug programs in user systems that have memory management mechanisms and cache functions, including timing. be.

[Brief explanation of drawings]

1 and 2 are block diagrams showing first and second embodiments of the present invention, respectively. 1.1a... Interrupt signal generation section, 2...
・Interrupt control unit, 3...- Internal memory, 4, 4a
...Emulation processor, 5...
...Distribution! , 6 , 6 a... Mapping circuit, 7 to 9... Buffer circuit, 10...
User system, 11...Interrupt timing generation unit, 12...Interrupt controller, 13゜1
3a... Interrupt vector storage section, 21...
・Interrupt prohibition switch, 22...OR gate,
23...AND gate. Agent: Susumu Uchihara, patent attorney

Claims (1)

[Claims] an interrupt signal generation unit that generates an interrupt signal at a predetermined timing based on set conditions; an interrupt control unit that selects either the interrupt signal from the interrupt signal generation unit or the interrupt signal from the user system side; an interrupt vector storage unit that outputs a preset interrupt vector based on the interrupt signal; and an internal unit that stores at least a debugged program and an interrupt processing program at predetermined addresses and reads out the programs at these addresses in accordance with the address signal. The program to be debugged is read and executed from the internal memory by sequentially outputting an address signal of an address in which the program to be debugged is normally stored, and when the interrupt signal is input, the interrupt vector is read and executed. and an emulation processor that outputs an address signal corresponding to an interrupt vector to read and execute the interrupt processing program from the internal memory, and returns to execution of the program to be debugged once execution of the interrupt processing program is finished. In-circuit emulator.