JPS6275542U - - Google Patents
Info
- Publication number
- JPS6275542U JPS6275542U JP16719885U JP16719885U JPS6275542U JP S6275542 U JPS6275542 U JP S6275542U JP 16719885 U JP16719885 U JP 16719885U JP 16719885 U JP16719885 U JP 16719885U JP S6275542 U JPS6275542 U JP S6275542U
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- memory
- control section
- emulator
- development support
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
- 239000000700 radioactive tracer Substances 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第1図は本考案を適用したマイクロプロセツサ
開発支援装置のエミユレーシヨン部のブロツク図
、第2図は本考案を説明するフローチヤート図で
ある。第3図は従来の開発支援装置のブロツク図
である。
1……スーパバイザ部、2……エミユレーシヨ
ン・メモリ、3……ブレーク・ポイント回路部、
4……リアル・タイム・トレーサ部、5……エミ
ユレーシヨン部、6……ターゲツト・システム、
7……スーパバイザ・バス、8……エミユレーシ
ヨン・プロセツサ・バス、9……本考案によるエ
ミユレータ・マイクロプロセツサ、10……命令
実行時間制御部。
FIG. 1 is a block diagram of an emulation section of a microprocessor development support system to which the present invention is applied, and FIG. 2 is a flowchart illustrating the present invention. FIG. 3 is a block diagram of a conventional development support device. 1...Supervisor section, 2...Emulation memory, 3...Break point circuit section,
4... Real time tracer section, 5... Emulation section, 6... Target system,
7...Supervisor bus, 8...Emulation processor bus, 9...Emulator microprocessor according to the present invention, 10...Instruction execution time control section.
Claims (1)
リを含むエミユレータ・マイクロプロセツサと該
エミユレータ・マイクロプロセツサの前記メモリ
の格納内容を変更する制御部と該制御部を管理す
るスーパバイサ・プロセツサを有するマイクロプ
ロセツサ開発支援装置。 A microprocessor comprising an emulator microprocessor including a memory for storing data for setting an instruction execution time, a control section for changing the contents stored in the memory of the emulator microprocessor, and a supervisor processor for managing the control section. Setsa development support equipment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16719885U JPH0229455Y2 (en) | 1985-10-29 | 1985-10-29 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16719885U JPH0229455Y2 (en) | 1985-10-29 | 1985-10-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6275542U true JPS6275542U (en) | 1987-05-14 |
JPH0229455Y2 JPH0229455Y2 (en) | 1990-08-08 |
Family
ID=31098903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16719885U Expired JPH0229455Y2 (en) | 1985-10-29 | 1985-10-29 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0229455Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63289653A (en) * | 1987-05-21 | 1988-11-28 | Nec Corp | In-circuit emitter |
-
1985
- 1985-10-29 JP JP16719885U patent/JPH0229455Y2/ja not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63289653A (en) * | 1987-05-21 | 1988-11-28 | Nec Corp | In-circuit emitter |
Also Published As
Publication number | Publication date |
---|---|
JPH0229455Y2 (en) | 1990-08-08 |
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