JPS61192352U - - Google Patents
Info
- Publication number
- JPS61192352U JPS61192352U JP7733685U JP7733685U JPS61192352U JP S61192352 U JPS61192352 U JP S61192352U JP 7733685 U JP7733685 U JP 7733685U JP 7733685 U JP7733685 U JP 7733685U JP S61192352 U JPS61192352 U JP S61192352U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- pointer
- list
- memory section
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案に適用されるメモリ構成の一具
体例を示す図、第２図は第１図に示したメモリ構
成をモデル化した図、第３図は本考案に適用され
るリストの一具体例を説明するための図、第４図
は本考案によるリスト・アクセス回路の一実施例
を示すブロツク図である。
２０……データ部、２０１……左ポインタ部、
２０２……右ポインタ部、３００〜３０６……リ
ストに含まれるデータ、４０……アドレス・ラツ
チ・セレクト部、４０１……アドレス出力、４１
……メモリ部、４１１……左ポインタ出力、４１
２……右ポインタ出力、４１３……データ出力、
４２……アドレス・バス、４２１……アドレス・
バス出力、４３……コントロール・バス、４３１
……コントロール・バス出力、４４……データ・
バス。
Figure 1 is a diagram showing a specific example of a memory configuration applied to the present invention, Figure 2 is a diagram modeling the memory configuration shown in Figure 1, and Figure 3 is a diagram showing a list applied to the present invention. FIG. 4 is a block diagram showing an embodiment of the list access circuit according to the present invention. 20...Data section, 201...Left pointer section,
202...Right pointer section, 300-306...Data included in list, 40...Address latch select section, 401...Address output, 41
...Memory section, 411 ...Left pointer output, 41
2...Right pointer output, 413...Data output,
42...Address bus, 421...Address bus
Bus output, 43...Control bus, 431
...Control bus output, 44...Data
bus.
Claims (1)
リ・アクセス回路において、データ、左ポインタ
および右ポインタを１組としたリスト構造を表現
するメモリ部と、ＣＰＵからアドレス・バスを介
して送られてくるアドレス、前記メモリ部から出
力される左ポインタおよび右ポインタの合計３種
類のアドレスを切換え、前記メモリ部に供給する
アドレスラツチ・セレクト回路とから構成したこ
とを特徴とするリスト・アクセス回路。 In a memory access circuit in a computer that performs a list process, a memory section representing a list structure including data, a left pointer and a right pointer as a set, an address sent from the CPU via an address bus, and the memory 1. A list access circuit comprising an address latch/select circuit for switching a total of three types of addresses, a left pointer and a right pointer output from the memory section, and supplying the selected addresses to the memory section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7733685U JPS61192352U (en) | 1985-05-24 | 1985-05-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7733685U JPS61192352U (en) | 1985-05-24 | 1985-05-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61192352U true JPS61192352U (en) | 1986-11-29 |
Family
ID=30620312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7733685U Pending JPS61192352U (en) | 1985-05-24 | 1985-05-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61192352U (en) |
-
1985
- 1985-05-24 JP JP7733685U patent/JPS61192352U/ja active Pending
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