JPS5949252U - address control device - Google Patents
address control deviceInfo
- Publication number
- JPS5949252U JPS5949252U JP12199083U JP12199083U JPS5949252U JP S5949252 U JPS5949252 U JP S5949252U JP 12199083 U JP12199083 U JP 12199083U JP 12199083 U JP12199083 U JP 12199083U JP S5949252 U JPS5949252 U JP S5949252U
- Authority
- JP
- Japan
- Prior art keywords
- processor
- address
- address control
- memory
- data bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のアドレス制御方式におけるプログラムエ
リアの一例を示す説明図、第２図は本考案に係るアドレ
ス制御方式の一実施例を示すう゛ロック結線図である。
３、 ４． ５・・・・・・メモリエリア、６・・・・
・・コンピュータ、？、 ８． ９・・・・・・アド
レス制御回路、１０・・・・・・入出力ポート、１１・
・・・・・選択回路、１２ａ。
１２ｂ・・・・・・アドレスバス、１３ａ、１３ｂ・・
・・・・データバス。FIG. 1 is an explanatory diagram showing an example of a program area in a conventional address control method, and FIG. 2 is a block diagram showing an embodiment of the address control method according to the present invention. 3, 4. 5...Memory area, 6...
··Computer,? , 8. 9... Address control circuit, 10... Input/output port, 11.
...Selection circuit, 12a. 12b...address bus, 13a, 13b...
...Data bus.
Claims (1)
前記プロセッサの固定プログラムを格納し前記データバ
スに直接接続された第一のメモリと、前記第一のメモリ
と同一のアドレス空間を有し前記プロセッサのジョブプ
ログラムを格納しかつ前記データバスに接続された第二
のメモリと、前記第一および第二のメモリのアドレス制
御を行ないかつ前記アドレスに並列に設けられた第一お
よび第二のアドレス制御回路と、前記第一および第二の
アドレス制御回路のどちらか一方に作動信号を与える選
択回路と、前記アドレスバスおよびデータバスに接続さ
れ前記固定プログラムまたは前記ジョブプログラムを実
行する前記プロセッサからの命令によって前記選択回路
を制御する人出カポートとを具備し、前記プロセッサが
前記第一および第二のメモリのどちらか一方を同一アド
レスでアクセスすることを特徴とするアドレス制御装置
。a processor having an address bus and a data bus;
a first memory that stores a fixed program for the processor and is directly connected to the data bus; and a first memory that stores a job program for the processor and has the same address space as the first memory and is connected to the data bus. a second memory; first and second address control circuits that perform address control of the first and second memories and are provided in parallel with the addresses; and the first and second address control circuits. a selection circuit that provides an activation signal to either one of the above, and a turntable port that is connected to the address bus and the data bus and controls the selection circuit in accordance with an instruction from the processor that executes the fixed program or the job program. An address control device, wherein the processor accesses one of the first and second memories using the same address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12199083U JPS5949252U (en) | 1983-08-04 | 1983-08-04 | address control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12199083U JPS5949252U (en) | 1983-08-04 | 1983-08-04 | address control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5949252U true JPS5949252U (en) | 1984-04-02 |
Family
ID=30279007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12199083U Pending JPS5949252U (en) | 1983-08-04 | 1983-08-04 | address control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5949252U (en) |
-
1983
- 1983-08-04 JP JP12199083U patent/JPS5949252U/en active Pending
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