JPS59108951U

JPS59108951U - information processing equipment

Info

Publication number: JPS59108951U
Application number: JP234383U
Authority: JP
Inventors: 室井　重治
Original assignee: 日本信号株式会社
Priority date: 1983-01-12
Filing date: 1983-01-12
Publication date: 1984-07-23

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案にかかる情報処理装置の１例を示す電気
回路のブロック図、第２図は制御卓の１例を示す電気回
路のブロック図、第３図は制御卓のパネルの１例を示す
図である。１：メインプロセッサ、２：ローカルプロセッサ、４　
、ＭＰＵ用メモリ、５　：ＬＰＵ用メモリ、６：制御卓
、７：データバス、８ニアドレスバス、１１：メモリ指
定ライン、１２：書込み指定ライン、１３：読出し指定
ライン、１５：バス開放指定ライン、２１：メモリ指定
スイッチ、２２：書込み指定セスイッチ、２３：読出し
指定スイッチ、２５：バス開放接続スイッチ、２６：デ
ータ表示灯、２７：データ設定スイッチ、２８ニアドレ
ス設定スイツチ。Fig. 1 is a block diagram of an electric circuit showing an example of an information processing device according to the present invention, Fig. 2 is a block diagram of an electric circuit showing an example of a control console, and Fig. 3 is an example of a panel of the control console. FIG. 1: Main processor, 2: Local processor, 4
, MPU memory, 5: LPU memory, 6: Control console, 7: Data bus, 8 Near address bus, 11: Memory designation line, 12: Write designation line, 13: Read designation line, 15: Bus release designation line , 21: Memory designation switch, 22: Write designation switch, 23: Read designation switch, 25: Bus open connection switch, 26: Data indicator, 27: Data setting switch, 28 Near address setting switch.

Claims

[Scope of utility model registration request]

A main processor, a local processor, a memory dedicated to the main processor, a memory dedicated to the local processor, and at least one control console are connected by a data bus, an address bus, and a write/read designation line, The console specifies a data indicator light and a data setting switch connected to the data bus, an address setting switch connected to the address bus, a write/read designation switch connected to the write/read designation line, and a memory. a memory designation switch; and a bus release designation switch for designating bus release; the memory designation switch is connected to the main processor, the local processor, and both memories via a memory designation line; An information processing device comprising: a switch connected to the main processor and the local processor via a bus open designation line.