JPS60167462U - Image processing device - Google Patents

Image processing device

Info

Publication number
JPS60167462U
JPS60167462U JP5440284U JP5440284U JPS60167462U JP S60167462 U JPS60167462 U JP S60167462U JP 5440284 U JP5440284 U JP 5440284U JP 5440284 U JP5440284 U JP 5440284U JP S60167462 U JPS60167462 U JP S60167462U
Authority
JP
Japan
Prior art keywords
data bus
image memory
processing circuit
processing
image processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5440284U
Other languages
Japanese (ja)
Inventor
尾形 伸治
毅 久保
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP5440284U priority Critical patent/JPS60167462U/en
Publication of JPS60167462U publication Critical patent/JPS60167462U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例のブロック図、また第2図は本考案−実
施例のブロック図を示す。 これらの図において、1は画像メモリ、2はデータバス
、3はドライバレシーバ、4は処理回路、9は専用デー
タバス、1Gはゲート、11は処理制御回路である。
FIG. 1 shows a block diagram of a conventional example, and FIG. 2 shows a block diagram of an embodiment of the present invention. In these figures, 1 is an image memory, 2 is a data bus, 3 is a driver receiver, 4 is a processing circuit, 9 is a dedicated data bus, 1G is a gate, and 11 is a processing control circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 画像メモリと、データバスと、前記画像メモリとデータ
バスとの間に設けられ画像メモリのデータの送出と受は
取り・とをおこなうドライバレシーバと、画像の拡大あ
るいは線描を含む処理を行う処理回路と、前記画像メモ
リから前記処理回路に対する専用データバスと、前記処
理回路と前記データバスとの間に設けられるゲートと、
前記処理回路が行う処理の内容に応じて前記ドライバレ
シーバとゲートとを制御する制御回路とを備えることを
特徴とする画像処理装置。
an image memory, a data bus, a driver receiver that is provided between the image memory and the data bus and sends and receives data from the image memory, and a processing circuit that performs processing including image enlargement or line drawing. a dedicated data bus from the image memory to the processing circuit, and a gate provided between the processing circuit and the data bus;
An image processing apparatus comprising: a control circuit that controls the driver receiver and the gate according to the content of processing performed by the processing circuit.
JP5440284U 1984-04-13 1984-04-13 Image processing device Pending JPS60167462U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5440284U JPS60167462U (en) 1984-04-13 1984-04-13 Image processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5440284U JPS60167462U (en) 1984-04-13 1984-04-13 Image processing device

Publications (1)

Publication Number Publication Date
JPS60167462U true JPS60167462U (en) 1985-11-07

Family

ID=30576127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5440284U Pending JPS60167462U (en) 1984-04-13 1984-04-13 Image processing device

Country Status (1)

Country Link
JP (1) JPS60167462U (en)

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