JPS59134972U - signal transmission circuit - Google Patents

signal transmission circuit

Info

Publication number
JPS59134972U
JPS59134972U JP2777783U JP2777783U JPS59134972U JP S59134972 U JPS59134972 U JP S59134972U JP 2777783 U JP2777783 U JP 2777783U JP 2777783 U JP2777783 U JP 2777783U JP S59134972 U JPS59134972 U JP S59134972U
Authority
JP
Japan
Prior art keywords
transmission circuit
signal transmission
signal
gate circuit
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2777783U
Other languages
Japanese (ja)
Inventor
曽根田　光生
裕司 林
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP2777783U priority Critical patent/JPS59134972U/en
Publication of JPS59134972U publication Critical patent/JPS59134972U/en
Pending legal-status Critical Current

Links

Landscapes

  • Liquid Crystal Display Device Control (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Details Of Television Scanning (AREA)
  • Electronic Switches (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

墳１図〜第３呻よ従来の回路の説明のための図、第４図
は本考案の一例の説明のための図、第５図〜第１０図は
応用例の説明のための図である。 １１は入力端子、１２はトランスファニゲート、１３は
制御端子、１４はコンデンサ、１５はトランジスタ、１
８は出力端子である。Figures 1 to 3 are diagrams for explaining the conventional circuit, Figure 4 is a diagram for explaining an example of the present invention, and Figures 5 to 10 are diagrams for explaining an example of application. be. 11 is an input terminal, 12 is a transfer gate, 13 is a control terminal, 14 is a capacitor, 15 is a transistor, 1
8 is an output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 映像信号に関連した入力信号を、クロック信号で駆動さ
れるゲート回路を介してサンプリングして伝送する信号
伝送回路において、上記クロック信号を、上記映像信号
のブランキング区間で上記ゲート回路をオンする電位に
保持されるように制−御したこと今特徴とする信号伝送
回路。In a signal transmission circuit that samples and transmits an input signal related to a video signal via a gate circuit driven by a clock signal, the clock signal is applied to a potential that turns on the gate circuit during a blanking period of the video signal. The signal transmission circuit is characterized in that it is controlled so that it is maintained at
JP2777783U 1983-02-25 1983-02-25 signal transmission circuit Pending JPS59134972U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2777783U JPS59134972U (en) 1983-02-25 1983-02-25 signal transmission circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2777783U JPS59134972U (en) 1983-02-25 1983-02-25 signal transmission circuit

Publications (1)

Publication Number Publication Date
JPS59134972U true JPS59134972U (en) 1984-09-08

Family

ID=30158659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2777783U Pending JPS59134972U (en) 1983-02-25 1983-02-25 signal transmission circuit

Country Status (1)

Country Link
JP (1) JPS59134972U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63219280A (en) * 1987-03-09 1988-09-12 Hitachi Ltd Driving circuit for matrix picture display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63219280A (en) * 1987-03-09 1988-09-12 Hitachi Ltd Driving circuit for matrix picture display device

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