JPS58166294U - Through current prevention circuit - Google Patents

Through current prevention circuit

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Publication number
JPS58166294U
JPS58166294U JP6258782U JP6258782U JPS58166294U JP S58166294 U JPS58166294 U JP S58166294U JP 6258782 U JP6258782 U JP 6258782U JP 6258782 U JP6258782 U JP 6258782U JP S58166294 U JPS58166294 U JP S58166294U
Authority
JP
Japan
Prior art keywords
prevention circuit
current prevention
current
delays
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6258782U
Other languages
Japanese (ja)
Inventor
古賀 恒繁
等 落合
Original Assignee
セイコーインスツルメンツ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーインスツルメンツ株式会社 filed Critical セイコーインスツルメンツ株式会社
Priority to JP6258782U priority Critical patent/JPS58166294U/en
Publication of JPS58166294U publication Critical patent/JPS58166294U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例のドライバー回路図、第2図は本考案の
実施例を示すドライバー回路図、第3図は本考案の実施
例による動作タイムチャート図である。 5・・・・・・Pチャネルトランジスタ、6・・・・・
・Nチャネルトランジスタ、8・・・・・・ORゲート
、9・・・・・・  。 ANDゲート。
FIG. 1 is a driver circuit diagram of a conventional example, FIG. 2 is a driver circuit diagram showing an embodiment of the present invention, and FIG. 3 is an operation time chart according to an embodiment of the present invention. 5...P channel transistor, 6...
・N-channel transistor, 8...OR gate, 9... AND gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ドライバー用トランジスタに入力する信号を遅延させ、
トランジスタの同時のON時間を少なくし、貫通電流を
おさえることを特徴とする貫通電流防止回路。
Delays the signal input to the driver transistor,
A through-current prevention circuit characterized by reducing the simultaneous ON time of transistors and suppressing through-current.
JP6258782U 1982-04-28 1982-04-28 Through current prevention circuit Pending JPS58166294U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6258782U JPS58166294U (en) 1982-04-28 1982-04-28 Through current prevention circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6258782U JPS58166294U (en) 1982-04-28 1982-04-28 Through current prevention circuit

Publications (1)

Publication Number Publication Date
JPS58166294U true JPS58166294U (en) 1983-11-05

Family

ID=30072735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6258782U Pending JPS58166294U (en) 1982-04-28 1982-04-28 Through current prevention circuit

Country Status (1)

Country Link
JP (1) JPS58166294U (en)

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