JPS5811258U - integrated circuit - Google Patents
integrated circuitInfo
- Publication number
- JPS5811258U JPS5811258U JP10518181U JP10518181U JPS5811258U JP S5811258 U JPS5811258 U JP S5811258U JP 10518181 U JP10518181 U JP 10518181U JP 10518181 U JP10518181 U JP 10518181U JP S5811258 U JPS5811258 U JP S5811258U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- transistor
- mos transistor
- type substrate
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本発明の一実施例を示す部分回路図、第２図は
第１図の出力バッファ部がＮチャネルＳｉデー１−ＭＯ
３集積回路で構成された場合のパターン図である。
１・・・・・・ＭＯ３集積回路の出力端子、２・・・・
・・Ｐ型基盤ＮチャネルエンハンスメントＭＯＳトラン
ジスタ、３・・・・・・Ｐ型基盤Ｎチャネルエンハンス
メントＭＯＳトランジスタ、４・・・・・・Ｐ型基盤Ｎ
チャネルデプレッションＭＯＳトランジスタ、５・・・
・・・Ｐ型基盤Ｎチャ・ネルエンハンスメントＭＯＳト
ランジスタ、６・・・・・・切換機構、７・・・・・・
出力バッファの入力信号（逆相）。FIG. 1 is a partial circuit diagram showing one embodiment of the present invention, and FIG. 2 shows that the output buffer section of FIG. 1 is an N-channel Si data 1-MO
FIG. 3 is a pattern diagram when the circuit is configured with three integrated circuits. 1... Output terminal of MO3 integrated circuit, 2...
... P-type substrate N-channel enhancement MOS transistor, 3 ... P-type substrate N-channel enhancement MOS transistor, 4 ... P-type substrate N
Channel depression MOS transistor, 5...
...P-type substrate N-channel enhancement MOS transistor, 6...Switching mechanism, 7...
Input signal of output buffer (negative phase).
Claims (1)
ト・トランジスタのゲートをこのトランジスタのしゃ断
電位に固定する手段を設けたことを特徴とする集積回路
。1. An integrated circuit comprising means for fixing the gate of an enhancement transistor as a load constituting an output of the integrated circuit to a cutoff potential of the transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10518181U JPS5811258U (en) | 1981-07-15 | 1981-07-15 | integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10518181U JPS5811258U (en) | 1981-07-15 | 1981-07-15 | integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5811258U true JPS5811258U (en) | 1983-01-25 |
Family
ID=29899725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10518181U Pending JPS5811258U (en) | 1981-07-15 | 1981-07-15 | integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5811258U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6073690U (en) * | 1983-10-28 | 1985-05-23 | 川崎重工業株式会社 | Step mounting structure |
| JPS60104817U (en) * | 1983-12-23 | 1985-07-17 | 松下電工株式会社 | X-ray film observation device |
| JPS63292647A (en) * | 1987-05-26 | 1988-11-29 | Fuji Xerox Co Ltd | Semiconductor integrated circuit device |
| JPH02262716A (en) * | 1989-04-03 | 1990-10-25 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
-
1981
- 1981-07-15 JP JP10518181U patent/JPS5811258U/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6073690U (en) * | 1983-10-28 | 1985-05-23 | 川崎重工業株式会社 | Step mounting structure |
| JPS60104817U (en) * | 1983-12-23 | 1985-07-17 | 松下電工株式会社 | X-ray film observation device |
| JPS63292647A (en) * | 1987-05-26 | 1988-11-29 | Fuji Xerox Co Ltd | Semiconductor integrated circuit device |
| JPH02262716A (en) * | 1989-04-03 | 1990-10-25 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6066049U (en) | C-MOS field effect transistor | |
| JPS58103153U (en) | Integrated circuit for inverting binary logic signals | |
| JPS5811258U (en) | integrated circuit | |
| JPS5996937U (en) | Schmitt trigger circuit | |
| JPS58166294U (en) | Through current prevention circuit | |
| JPS5893014U (en) | Complementary output circuit | |
| JPS5861538U (en) | latch circuit | |
| JPS60174333U (en) | analog switch | |
| JPS5988922U (en) | differential amplifier | |
| JPS6133517U (en) | Muting circuit | |
| JPS59111334U (en) | inverter circuit | |
| JPS5988923U (en) | differential amplifier | |
| JPS6067600U (en) | semiconductor circuit | |
| JPS6045532U (en) | transistor circuit | |
| JPS58165800U (en) | EPROM writing circuit | |
| JPS59129210U (en) | transistor circuit | |
| JPS5897800U (en) | memory device | |
| JPS58186634U (en) | signal switching device | |
| JPS5844613U (en) | Reference current source circuit | |
| JPS5952733U (en) | D/A converter output buffer circuit | |
| JPS5995390U (en) | Output circuit | |
| JPS58141608U (en) | differential amplifier circuit | |
| JPS59177232U (en) | latch circuit | |
| JPS5834412U (en) | Output buffer circuit | |
| JPS5929817U (en) | AGC circuit |