JPS59129210U - transistor circuit - Google Patents
transistor circuitInfo
- Publication number
- JPS59129210U JPS59129210U JP1484U JP1484U JPS59129210U JP S59129210 U JPS59129210 U JP S59129210U JP 1484 U JP1484 U JP 1484U JP 1484 U JP1484 U JP 1484U JP S59129210 U JPS59129210 U JP S59129210U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- type mis
- output
- high impedance
- enhancement type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のトランジスタ増幅回路、第２図は従来の
トランジスタの増幅回路の１応用例、第３図ＡおよびＢ
は本考案にかかるトランジスタ増幅回路、第４図は第３
図ＡおよびＢに示す回路において用いられるデプレッシ
ョントランジスタの定電流特性を示す図である。第３図
ＡおよびＢにおいて、２３ａおよび２３ｂがデプレッシ
ョントランジスタである。Figure 1 shows a conventional transistor amplifier circuit, Figure 2 shows an example of an application of a conventional transistor amplifier circuit, and Figure 3 A and B.
4 is a transistor amplifier circuit according to the present invention, and FIG. 3 is a transistor amplifier circuit according to the present invention.
3 is a diagram showing constant current characteristics of a depletion transistor used in the circuits shown in FIGS. A and B. FIG. In FIGS. 3A and 3B, 23a and 23b are depletion transistors.
Claims (1)
状態を含む３値の出力を生じる増幅回路であって、且つ
前記複数個の増幅回路のうちの最大１個の出力のみが０
°°あるいは゛１′出力を許され他の出力は高インピー
ダンスであるべき増幅回路であって、出力端と高電位側
電源線との間に直列に接続された第１のエンハンスメン
ト型ＭＩＳ）ランジスタ、デプレッション型ＭＩＳトラ
ンジスタと、前記出力端と低電位側電源線との間に接続
された第２のエンハンスメント型ＭＩＳ ）ランジスタ
とを有し、前記第１、第２のエンハンスメント型ＭＩＳ
）ランジスタは入力信号をゲートに受け、前記デプレッ
ション型ＭＩＳトランジスタはゲートとソースが共通接
続され、前記゛１′を出力している際中に出力状態が高
インピーダンス状態となっていない他の増幅回路へ前記
第１のエンハンスメント型Ｍｉｓ）ランジスタから前記
パスラインを介して流れる電流を制限できるようにした
ことを特徴とするトランジスタ回路。A plurality of amplifier circuits are connected to a common path line and produce three-value outputs including a high impedance state, and the output of at most one of the plurality of amplifier circuits is 0.
The first enhancement type MIS is an amplifier circuit that is allowed to output °° or '1' and other outputs must be high impedance, and is connected in series between the output terminal and the high potential side power supply line. transistor, a depletion type MIS transistor, and a second enhancement type MIS transistor connected between the output terminal and the low potential side power supply line;
) The transistor receives an input signal at its gate, the gate and source of the depletion type MIS transistor are commonly connected, and the output state is not in a high impedance state while outputting the above-mentioned "1". A transistor circuit characterized in that the current flowing from the first enhancement type Mis) transistor through the pass line can be limited.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1484U JPS59129210U (en) | 1984-01-05 | 1984-01-05 | transistor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1484U JPS59129210U (en) | 1984-01-05 | 1984-01-05 | transistor circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59129210U true JPS59129210U (en) | 1984-08-30 |
Family
ID=30131755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1484U Pending JPS59129210U (en) | 1984-01-05 | 1984-01-05 | transistor circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59129210U (en) |
-
1984
- 1984-01-05 JP JP1484U patent/JPS59129210U/en active Pending
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