JPS5942639U

JPS5942639U - comparator

Info

Publication number: JPS5942639U
Application number: JP13786282U
Authority: JP
Inventors: 仲山　芳郎; 安部　文紀; 長沢　尚文
Original assignee: 三洋電機株式会社
Priority date: 1982-09-10
Filing date: 1982-09-10
Publication date: 1984-03-19
Also published as: JPH026679Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は一般的なＡＤ変換器を示すブロック図、第２図
イ及び第３図イは各々従来のＮ型コンパレータ及びＰ型
コンパレータを示す回路図、第２図口及び第３図町よ各
々従来のＮ型コンパレータ及びＰ型コンパレータを第１
図のＡＤ変換器に使用した場合の入力電圧Ｖｉとカウン
タ出力り。との関係を示す特性図、第４図は本考案の実
施例を示すブロック図である。主な図番の説明、１・・・コンパレータ、２・・・フリ
ップフロップ、３・・・クロック発振器、４・・・カラ
ン　２夕、５・・・ＤＡ変換器、８，１１・・・差動対
、１２゜１３・・・反転入力端子、１４．１５・・・非
反転入力端子、１８・・・コンパレータ、１９・・・Ｎ
型コンパレータ、２０・・・Ｐ型コンパレータ、２１．
２２・・・Ａ、ＮＤゲート、２３・・・ＯＲゲート、２
４・・・制御端子、２５・・・出力端子。Figure 1 is a block diagram showing a general AD converter, Figure 2 A and Figure 3 A are circuit diagrams showing a conventional N-type comparator and P-type comparator, respectively. The conventional N-type comparator and P-type comparator are respectively
Input voltage Vi and counter output when used in the AD converter shown in the figure. FIG. 4 is a block diagram showing an embodiment of the present invention. Explanation of main figure numbers, 1...Comparator, 2...Flip-flop, 3...Clock oscillator, 4...Calan 2, 5...DA converter, 8, 11...Difference Dynamic pair, 12゜13...Inverting input terminal, 14.15...Non-inverting input terminal, 18...Comparator, 19...N
Type comparator, 20...P type comparator, 21.
22...A, ND gate, 23...OR gate, 2
4...Control terminal, 25...Output terminal.

Claims

[Scope of utility model registration request]

An N-type comparator and a P-type comparator each having a differential pair formed of N-type and P-type enhancement transistors, and a first and a second inverting input terminal common to the inverting input terminal and non-inverting input terminal of both comparators, respectively. first and second input terminals that supply an input signal; and first and second logic circuits that input the outputs of both the comparators to one end of the input terminal, and input a control signal and an inverted signal of the signal to the other end of the logic circuit. A structure consisting of a product circuit and an OR circuit inputting the outputs of the two-wheel buried circuit.
A comparator, characterized in that the outputs of the N-type comparator and the P-type comparator are switched according to the control signal and are derived from the OR circuit.