JPH026679Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field The present invention relates to a comparator using MOS transistors, and particularly relates to a comparator that is optimal for an AD converter.

(b) Background technology In general, an AD converter, as shown in Figure 1,
It consists of a comparator 1, a flip-flop 2, a clock oscillator 3, a counter 4, and a DA converter 5, and the analog voltage Vi to be converted is input to the comparator 1. Then, first, the conversion start signal
When ST occurs, the counter 4 and flip-flop 2 are reset, the clock oscillator 3 starts oscillating, and the counter 4 counts the clock pulse CL and its content increases. The contents of the counter 4 are converted into an analog voltage _V0 by the DA converter 5, and when this voltage _V0 slightly exceeds the input analog voltage Vi, the output C of the comparator 1 becomes "H", setting the flip-flop 2. . Therefore, the Q output becomes "H" and the oscillation of the clock oscillator 3 stops, and the contents of the counter 4 stop when the output voltage _V0 of the DA converter and the input analog voltage Vi become approximately equal. That is, a digital signal corresponding to the input analog voltage Vi is obtained as the output _D0 of the counter 4.

In this way, comparators are generally used in AD converters, but comparators using MOS transistors include an N-type comparator with the configuration shown in Figure 2A, and a P-type comparator with the configuration shown in Figure 3A.
Type comparators are commonly used. This N-type comparator and P-type comparator are connected to the power supply voltage
A differential pair 8 consisting of N-type transistors 6, 7 and P-type transistors 9, 10 are connected between V _DD and V _SS .
Input voltages are applied to the gates of the MOS transistors constituting these differential pairs 8 and 11 from inverting input terminals 12 and 13 and inverting input terminals 14 and 15, respectively. Vi and _V0 are input. In addition, in FIG. 2A and FIG. 3A, the N-type transistor 16 and the P-type transistor 17 are each constant current sources to which a predetermined bias voltage Vb is applied to the gate.

However, in conventional N-type comparators and P-type comparators, N-type transistors 6 and 7 and P-type transistors 9 and 10 that constitute differential pairs 8 and 11 are all enhancement type transistors.
Since it is formed of MOS transistors, in the case of an N-type comparator, the output C becomes unstable for an input voltage below the threshold voltage Vt _N of the N-type transistors 6 and 7, and even in the case of a P-type comparator, If the threshold voltage of the P-type transistors 9 and 10 is Vtp, there is still a drawback that the output C becomes unstable for input voltages equal to or higher than V _DD -Vt _P. That is, a dead zone existed.

Therefore, when an N-type comparator is used in an AD converter as shown in Fig. 1, as shown in Fig. 2 (b), if the input voltage Vi is equal to or higher than the threshold voltage _Vt Input voltage as D ₀
A digital signal corresponding to Vi is obtained, but Vt _N
In the following, the output D ₀ is not determined, and even when a P-type comparator is used, the input voltage Vi is V _DD −Vt _P
In the above case, there was a problem that the output D ₀ was not determined.

Therefore, in the past, a bias circuit was provided at the input section of the comparator or the input voltage was limited to avoid the dead zone of the comparator and operate the comparator.

(c) Purpose of the invention In view of the above-mentioned drawbacks, the present invention provides a new comparator that eliminates the dead zone by combining an N-type comparator and a P-type comparator.

(d) Embodiment FIG. 4 is a block diagram showing an embodiment of the comparator according to the present invention, and shows the case where it is applied to a DA converter. In FIG. 4, numeral 18 is a comparator according to the present invention, and the rest of the configuration is exactly the same as the DA converter shown in FIG.

As shown in FIG. 4, the comparator 18 connects a differential pair composed of N-type enhancement type transistors and a differential pair composed of P-type enhancement type transistors between power supply voltages V _DD and V _SS . N-type comparator 19 (see Figure 3 A) and P-type comparator 20 (see Figure 2 A)
and the outputs of these comparators 19 and 20
It is composed of AND gates 21 and 22, which input C ₁ and C ₂ at one end, and a control signal G and its inverted signal at the other end, and an OR gate 23, which inputs the outputs of AND gates 21 and 22. The input analog voltage Vi to be converted is input to the inverting input terminals of the N-type comparator 19 and the P-type comparator 20, and the output voltage V ₀ of the DA converter 5 is input to the non-inverting input terminals.

Further, the counter 4 has a 4-bit configuration, and when the contents are all 0, the output voltage _V0 of the DA converter 5 is almost equal to the power supply voltage _VSS , and when the contents are all 1, the output voltage is
V ₀ is set to be approximately equal to the power supply voltage V _DD , and the fourth bit Q ₄ output of the counter 4 is input as the control signal G to the control terminal 24 of the comparator 18 . That is, when the output voltage V ₀ reaches approximately 1/2V _DD , the control signal G is inverted from "L" to "H".

Therefore, assuming that a voltage below the threshold voltage _VtN is input as the input analog voltage Vi, first, the counter 4 and flip-flop 2 are reset by the conversion start signal ST, so that
The output voltage of the DA converter 5 is approximately _VSS , the _Q4 output of the counter 4, that is, the control signal G is "L", and one ends of the AND gates 21 and 22 have "I" and "H" signals, respectively. will be applied.
In this state, the P-type comparator 20 operates reliably, its output _C2 becomes "L", and
Since the "H" signal is input to the other end of the AND gate 22, the output _C2 is connected to the AND gate 22 and
It is led out to the output terminal 25 via the OR gate 23. On the other hand, the N-type comparator 19 input voltage Vi
Since both V ₀ and V 0 are below the threshold voltage Vt _N , the output C ₁ is undefined, but the AND gate 2
Since the control signal G of "L" is input to C1, its output _C1 is blocked by the AND gate 21. Thereafter, the counter 4 counts up by the clock pulse CL, and when the output voltage _V0 slightly exceeds the input analog voltage Vi, the output _C2 of the P-type comparator 20 is inverted to "H" and the flip-flop 2 is set. The clock oscillator 3 stops oscillating, and the counter 4 stops counting up. Here, even if the output voltage V ₀ rises, it will not exceed the threshold voltage Vt _N , so the output C ₁ of the N-type comparator 19 will always be constant, but the Q ₄ output of the counter 4 will be inverted to "H". The control signal G remains "L" until the output voltage V ₀ reaches approximately 1/2V _DD .
The output C ₁ of the N-type comparator 19 continues to be blocked,
The output terminal 25 is the output of the P-type comparator 20.
Only C ₂ will be derived.

Next, as the input analog voltage Vi, V _DD −Vt _P
Assuming that the above voltage is input, the output voltage V ₀ becomes approximately V _SS as described above, so the output C ₂ of the P-type comparator 20 and the N-type comparator 19
and C ₁ are both "L". Therefore, the content of the counter 4 increases, and the output voltage V ₀ also increases accordingly. Then, when the Q ₄ output of the counter 4 is inverted to "H", the output of the inverter 26 becomes "L", so that the output C ₂ of the P-type comparator 20 is blocked. That is, the output voltage
When V ₀ reaches approximately 1/2V _DD , P-type comparator 2
The output C ₁ of the N-type comparator 19 is now delivered to the output terminal ₂₅ instead of the output C 2 of 0.
Then, it further counts up and output voltage
When V ₀ becomes more than V _DD −Vt _P , the output C ₂ of the P-type comparator 20 becomes undefined, but the AND gate 22
Since the output C ₂ is blocked, the output C ₁ of the N-type comparator 19, which operates reliably, becomes the output C of the comparator 18 . And the output voltage
When V ₀ slightly exceeds the input analog voltage Vi,
The output _C1 of the N-type comparator 19 is inverted to "H" and the count-up is stopped.

As described above, the comparator 18 includes the P-type comparator 20 and the N-type comparator 19, and switches between the outputs C ₂ and C ₁ and outputs them to the output terminal 25 when the input voltage V ₀ is below or above 1/2V _DD . This makes it possible to eliminate the dead zone. Incidentally, in the above embodiment, the counter 4 is used as the control signal G.
_{Using the Q4 output of ​} It is sufficient to switch when a predetermined voltage is reached, and the voltage is not limited to 1/2V _DD .

(e) Effects As mentioned above, the comparator according to the present invention can eliminate the dead zone with a very simple configuration.
Therefore, there is no need to provide a bias circuit at the input section of the comparator or to limit the input voltage. Therefore, the capacitive load on the input terminal of the comparator is reduced and circuit design becomes easier.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a general DA converter, Figures 2A and 3A are circuit diagrams showing a conventional N-type comparator and P-type comparator, respectively, and Figures 2B and 3B are circuit diagrams. A characteristic diagram showing the relationship between the input voltage Vi and the counter output D ₀ when a conventional N-type comparator and a P-type comparator are used in the AD converter shown in FIG. 1. FIG. 4 shows an embodiment of the present invention. It is a block diagram. Explanation of main drawing numbers, 1... Comparator, 2...
Flip-flop, 3...Clock oscillator, 4...
... Counter, 5 ... DA converter, 8 , 11 ... Differential pair, 12, 13 ... Inverting input terminal, 14, 15
...Non-inverting input terminal, 18 ...Comparator, 1
9...N-type comparator, 20...P-type comparator, 21, 22...AND gate, 23...OR
Gate, 24...control terminal, 25...output terminal.

Claims (1)

[Claims for Utility Model Registration] An N-type comparator and a P-type comparator, each of which is configured with a differential pair of N-type and P-type enhancement transistors, and common to the inverting input terminal and non-inverting input terminal of both comparators, respectively. first and second input terminals for supplying first and second input signals to the comparators; and a first input terminal for inputting the outputs of both the comparators at one end thereof and inputting a control signal and an inverted signal of the signals at the other end, respectively. It is composed of first and second AND circuits, and an OR circuit that inputs the outputs of both AND circuits, and outputs an output according to the count value of a counting circuit that is controlled based on the output of the OR circuit. A comparator, which is used as the control signal to switch outputs of the N-type comparator and the P-type comparator according to the count value.