JP3094040B2 - CMOS logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit having a CMOS (complementary MOS) transistor structure, and more particularly to a CMOS logic circuit applicable to random logic and capable of operating at high speed with a low voltage power supply.

[0002]

2. Description of the Related Art The prior art is shown by an example of an inverter circuit in FIG. 11 is an input terminal, 12 is an output terminal, 13 is a voltage source having a voltage value _Vdd , 14 is a PMOS, 15 is an NMOS, 16
Is a load capacitance connected to the output terminal. The input signal conforms to the digital input value, and is at V _dd when the logic is “1” and at the GND level when the logic is “0”. V _thP the Suresshuhorudo voltage of the PMOS transistor and the Suresshuhorudo voltage of the NMOS transistor and V _thN, but not problems in sufficiently large if the circuit than V _dd is the V _thP or V _thN, V _dd is V _The operating speed becomes _{slower as} it approaches _thP or _VthN .

The operating speed of a logic circuit is determined by the charge / discharge time of the load capacitance 16 at the output terminal. Therefore, the larger the charge / discharge current of the load capacity (I _P , I _{N in} FIG. 6), the higher the speed. On the other hand, the current _Ids between the source and the drain of the MOS transistor is represented by α as a constant.

[0004]

(Equation 1)

[0005] In the conventional circuit, the maximum value of the gate-source voltage V _gs is V _dd , so that I _P and I _N are

[0006]

(Equation 2)

[0007] Thus (V _dd -V _thP) or (V _dd -V _thN) decreases as I _P, I _N is reduced in proportion to the square. For this reason, in the conventional circuit, there is a problem that when _Vdd is reduced, the operation speed is rapidly deteriorated and slowed down. In order to solve this problem, the present applicant has previously proposed the circuit shown in FIG. 7 (Japanese Patent Application No. 3-13107).
No. 1). That is, a circuit including the capacitor C1 and the resistor R1 between the input terminal 11 and the gate of the PMOS 14, and a capacitor C2 and the resistor R1 between the input terminal 11 and the gate of the NMOS 15.
2 and a voltage to be biased is applied to the terminals of the resistors R1 and R2, or the terminal of the resistor R1 is connected to G
The terminal of the resistor R2 is connected to ND and _Vdd . V _thN =
0.6 V, V _thP = 0.6 V, V _dd = 1 V, VR ₂ = 1
The operation of the circuit of FIG. 7 will be described below assuming that V, V _R1 = 0V, (V _R2 , V _R1 are terminal voltages of the resistors R2, R1).

Since the amplitude of the input signal is from the GND level to the _Vdd level, it is 0 to 1 V in this embodiment. The resistances of the resistors R1 and R2 are very large, and the potential differences V _C1 and V _C2 between both ends of the capacitors C1 and C2 do not change in a short time. Assuming that the appearance probabilities of the logic “1” and the logic “0” of the input signal are equal, the average voltage is V _dd / 2 =
It becomes 0.5V. Therefore, V _C1 becomes −0.5V and V _C2 becomes + 0.5V. When the potential difference between V _C1 and V _C2 is also taken into consideration when the input is 0 V, the gate voltage of the PMOS becomes −0.5.
V, the gate voltage of the NMOS is + 0.5V. At this time, V _gs of the PMOS becomes 1.5V. In the circuit of FIG.
_gs is 1V. Figure 7 A comparison of the I _P in this case is I _P
= Α · (1.5−0.6) ² = 0.81 · α, whereas in the circuit of FIG. 6, I _P = α · (1.0−0.6) ² = 0.
16 · α, and the current value of the circuit of FIG. 7 is 5 times,
At V _dd = 1 V, the circuit of FIG. 7 has an advantage that the speed can be increased by a factor of 5 compared to the generally used circuit of FIG.

[0009]

However, in the circuit of FIG. 7, V _C1 and V _C2 are determined on the premise that the appearance probabilities of “1” and “0” of the input data are equivalent, and the frequency divider Can be used for circuits such as the above, but the potential difference between V _C1 and V _C2 cannot be predicted with random logic in which the appearance probabilities of “0” and “1” are indeterminate, making it difficult to set V _R2 and V _R1. Have a point. In the previous example, “0” or “1” is input for a long time.
Is input, the gate voltage of the PMOS becomes 0 V and the gate voltage of the NMOS becomes 1 V, regardless of the input value, and both the PMOS and the NMOS are turned on and a through current flows. I was

An object of the present invention is to solve the above-mentioned problem in the circuit shown in FIG.
Applicable to random logic unrelated to the probability of appearance of
CMOS capable of realizing high-speed operation with low power supply voltage
It is to provide a logic circuit.

[0011]

According to a first aspect of the present invention, there is provided a CMO comprising a first PMOS transistor and a first NMOS transistor.
In the S logic circuit, the gate of the first PMOS is connected to the input terminal via the first capacitor, the drain is the output terminal, the source is the first voltage source _Vdd , and the gate of the first NMOS is the second. The input terminal via the capacitance, the drain to the output terminal,
The source is connected to a second voltage source GND, and further includes a second PMOS and a second NMOS for input bias,
A PMOS gate in a first PMOS gate, a drain to a first NMOS gate, for the first bias is set to the source to Suresshuhorudo voltage V _th is less than the positive voltage value V _s of the MOS transistor A second voltage source
The gate of the NMOS to the gate of the first NMOS, the drain to the gate of the first PMOS, and the source to the voltage value V _dd.
−V _s , which is connected to a second bias voltage source set to obtain an inverted signal of the input terminal signal at the output terminal.
It is assumed that the MOS logic circuit is used.

According to a second aspect of the present invention, the first
In the CMOS logic circuit including the PMOS transistor and the first NMOS transistor, the gate of the first PMOS is connected to the input terminal via the first capacitor, the drain is connected to the output terminal, and the source is connected to the first voltage source _Vdd . , The first NMO
A gate of S is connected to an input terminal via a second capacitor, a drain is connected to an output terminal, and a source is connected to a second voltage source GND;
Further, a second PMOS and a second NMO for input bias are used.
Has S, to the output terminal of the gate of the second NMOS, the gate of the first NMOS source, first set the drain Suresshuhorudo voltage V _th is less than the positive voltage value V _s of the MOS Toranjita 1 , The gate of the second PMOS to the output terminal, and the source to the first PMOS.
A CMOS logic circuit having a configuration in which a drain is connected to the gate of S and a drain is connected to a second bias voltage source set to a voltage value of V _dd -V _s to obtain an inverted signal of the input terminal signal at the output terminal.

[0013]

The CMOS logic circuit of the present invention is the same as the conventional circuit of FIG. 7 in that each gate of the PMOS and NMOS forming the CMOS is connected to the input terminal via a capacitor for cutting off the DC component of the signal. However, as a configuration for applying a bias potential to each gate, a second PMOS and a second NMOS
The provided, V _th> V _s> 0 and the first bias voltage source having a set voltage value V _s such that the voltage value V _dd -V _s
The configuration differs from the conventional CMOS logic circuit shown in FIG. 7 in that the source of the second PMOS and the second NMOS for bias is connected to the second bias voltage source having
The operation of the circuit will be described in detail in the following embodiments, giving specific numerical examples.

[0014]

FIG. 1 shows an embodiment of an inverter circuit according to claim 1 of the present invention. The connection is as follows. The input terminal 11 is connected to one terminal of the capacitors 21 and 22, the other terminal of the capacitor 21 is connected to the gate of the first PMOS 14 forming a CMOS, and the other terminal of the capacitor 22 is connected to the first terminal forming a CMOS.
To the gate of the NMOS 15. The source of the PMOS 14 is connected to the first voltage source 13 having the voltage value _Vdd and the NMOS 14
Is connected to the second voltage source GND, and the PMOS 14
And the drain of the NMOS 15 are connected to form the output terminal 12. Further, a second PMOS 31 and a second NMOS 32 for bias are provided.
The gate of the MOS 31 and the drain of the NMOS 32 are connected to NM
The drain of the PMOS 31 and the NMOS are connected to the gate of the OS 15
32, and the source of the PMOS 31 is connected to V _th
> The first voltage source 26 for biasing with V _s> 0 and so as to set voltage value V _s, the second voltage source for bias having a voltage V _dd -V _s source of NMOS32 25
Connect to

[0015] Terminal 11 is V _dd becomes when the input signal is a logic "1" to the input terminal 11, V ₂₁ the potential difference across the capacitor 21, when the potential difference across the capacitor 22 to V _22, the potential at point a Is V _dd + V ₂₁ , and the potential at point b is V _dd + V ₂₂ . At this time, the transistors 15 and 32 are turned on, and the transistors 14 and 31 are turned off. Therefore, the output goes to the GND level and outputs a logic "0" to operate the inverter. Further, since the transistor 32 is turned on, the potential at the point a is V _dd
−V _s and V ₂₁ is charged to −V _s . V ₂₂ at this time does not change because the transistors 31 is off. Next, when the input is logic "0", the terminal 11
D, point a is V ₂₁ , and point b is V ₂₂ . At this time, the transistors 14 and 31 are turned on, and the transistors 15 and 3 are turned on.
2 turns off. Since the transistor 14 is on and the transistor 15 is off, the output 12 becomes _Vdd and outputs a logic "1".
At this time, the transistor 31 is also because of the ON, b point is charged so as to become V _s. For this reason, V ₂₂ becomes V _s. At this time, V ₂₁ does not change because the transistor 32 is off. Thus, C ₂₁ and C ₂₂ are set so that V ₂₁ = −V _s and V ₂₂ = V _s regardless of the input data.
Is charged. Since V ₂₁ = −V _s and V ₂₂ = V _s , V _gs of the transistor 14 when the input 11 is at the GND level becomes V _dd + V _s and V _gs of the transistor 15 when the input 11 is at V _dd. V _dd + V _s , and V _gs is increased by V _s compared to the general logic circuit shown in FIG. 6, and the current drive capability of the output 12 is increased by that amount, so that high speed is possible.

As described above, when the present invention is used, the same effect as the conventional high-speed operation at a low power supply voltage shown in FIG. 7 can be obtained, and the voltages of V ₂₁ and V ₂₂ are changed to the input “0” “1”. Has the advantage of being applicable to all random logic because it can be set irrespective of the appearance probability of "".

FIG. 2 shows an example in which the above-described inverter circuit is applied to a two-input NAND circuit.
2, two circuits composed of a PMOS 31 and an NMOS 32, and a two-signal NAND input to input terminals 11 and 11 '.
It is configured to take logic and output to the output terminal 12.

FIG. 2 shows an embodiment having two inputs. However, the same configuration can be obtained even if the input is multi-input, and the same effect as in the case of FIG. 1 can be produced. Similarly, in the conventional two-input NOR circuit and multi-input NOR circuit, the capacitors 21 and 22, the PMOS 31, and the NMOS 31 shown in FIG.
A similar effect can be obtained by adding two or more sets of 32 circuits.

FIG. 3 shows an embodiment of the inverter circuit according to claim 2 of the present invention. In connection, capacity 21, 22,
The PMOS 14 and the NMOS 15 are the same as those in the embodiment shown in FIG. 1, except that the gates of the transistors 31 and 32 are connected to the output terminal 12. The operation of this circuit will be described using the same values as those in FIG. Input 1
When logic "0" is input to 1, 11 goes to the GND level, transistor 14 turns on, transistor 15 turns off, and output 12 goes to _Vdd . Thus transistor 31 is off, the transistor 32 is as the potential of the point b becomes ON is V _s, capacitor 22 is charged, and V ₂₂ = V _s. At this time, since the transistor 31 is off, V ₂₁
Does not change. When logic "1" is input to input 11, 1
1 becomes _Vdd , the transistor 14 is turned off, and the transistor 15 is turned on. Therefore, the output 12 is at the GND level. At this time, the transistor 31 is turned on and the transistor 3 is turned on.
2 turns off. Therefore capacitance 21 as the potential of the point a becomes V _dd -V _s is charged, and V ₂₁ = -V _s. At this time, the transistor 32 is not V ₂₂ is varied because it is off. As described above, according to this circuit, V ₂₁ = −V as in FIG.
_s , V ₂₂ = V _s, and the same effect can be obtained. Further, since the gates of the transistors 31 and 32 are connected to the output, the stray capacitance at points a and b is reduced.

FIG. 4 shows the inverter circuit of FIG.
This is an example in which the present invention is applied to a transfer gate (abbreviated as TG), where 11 is an input terminal of the TG, 12 is an output terminal of the TG, 6
1 is a positive phase control signal terminal, and 62 is a negative phase control signal terminal. The operation of this circuit is almost the same as that of FIG. 3, but the on / off control of the transistors 31 and 32 is performed by a complementary control signal.

FIG. 5 shows an embodiment in which the first and second aspects of the present invention are mixed, and the two-input N shown in FIG.
Claim 1 (FIG. 1) is applied to the gate on the NMOS side of the AND circuit.
In the PMOS side (FIG. 3).

[0022]

As described above, when the present invention is used, a random logic which operates at a high speed with a low power supply voltage can be realized, and a high power supply voltage cannot be obtained due to battery driving or the like. Is effective as an LSI logic circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of an inverter circuit according to claim 1 of the present invention.

FIG. 2 is an embodiment diagram in which the circuit of FIG. 1 is applied to a NAND circuit.

FIG. 3 is a diagram showing an embodiment of an inverter circuit according to claim 2 of the present invention.

FIG. 4 is an embodiment diagram in which claim 2 of the present invention is applied to a transfer gate.

FIG. 5 is an embodiment diagram in which claims 1 and 2 of the present invention are applied to a NAND circuit.

FIG. 6 is a conventional general inverter circuit diagram.

FIG. 7 is a conventional inverter circuit diagram for achieving high-speed operation at a low power supply voltage.

[Explanation of symbols]

21, 22 ... first, second capacitor 14, 15 ... first PMOS, the first NMOS 25 and 26 ... bias voltage source _{(V dd -V s, V s} ) 31,32 ... second PMOS , The second NMOS

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuo Aoyama 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 19 / 0948

Claims (2)

(57) [Claims] 1. A first PMOS transistor and a first NM
In a CMOS logic circuit composed of OS transistors,
The gate of the first PMOS is connected to the input terminal via the first capacitor, the drain is connected to the output terminal, and the source is connected to the first voltage source V _dd.
The gate of the first NMOS is connected to the input terminal via the second capacitor, the drain is connected to the output terminal, the source is connected to the second voltage source GND, and the second PMO for input bias is further connected.
S and a second NMOS, the gate of the second PMOS being the gate of the first PMOS, and the drain being the first NMOS.
The gate, the first bias voltage source set the source to Suresshuhorudo voltage V _th is less than the positive voltage value V _s of the MOS transistor, a gate of the second NMOS the first NMOS gate, The drain is the first PMOS
And a source connected to a second bias voltage source set to a voltage value of V _dd -V _s to obtain a reverse signal of an input terminal signal at an output terminal. 2. A first PMOS transistor and a first NM.
In a CMOS logic circuit composed of OS transistors,
The gate of the first PMOS is connected to the input terminal via the first capacitor, the drain is connected to the output terminal, and the source is connected to the first voltage source V _dd.
The gate of the first NMOS is connected to the input terminal via the second capacitor, the drain is connected to the output terminal, the source is connected to the second voltage source GND, and the second PMO for input bias is further connected.
Have the S and the second NMOS, the output terminal of the gate of the second NMOS, the gate of the first NMOS source and drain Suresshuhorudo voltage V _th is less than the positive voltage value V _s of the MOS Toranjita The set first bias voltage source, the gate of the second PMOS to the output terminal, the source to the gate of the first PMOS, and the drain to the voltage value V _dd.
Connected to a second bias voltage source set to -V _s, CMOS logic circuit, characterized in that to obtain the inverted signal of the input terminal signal to the output terminal.