JPH0458207B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level adjuster used when connecting circuits with different voltage levels. Conventional level adjusters have often been of the type consisting of a resistor and a transistor connected in series. However, devices using resistors have a slow response speed and voltage loss occurs within the resistor, so when used in circuits that need to save power consumption, especially wristwatches, it is desirable to have a circuit that consumes as little power as possible.

Due to these demands, Patent No. 54539 was issued in 1972.
As seen in the issue of Voltage Level Adjuster, an application has been filed for a level adjuster system with low power consumption that consists of complementary connected transistors and a diode and capacitor that clamp the gates of the transistors. This level adjuster malfunctions when the charge in the capacitor is discharged, so it has the disadvantage that it can only be used as a level adjuster for relatively high-speed signals.

However, since the level adjuster of the present invention is equipped with a memory circuit, it can level adjust a wide range of signals, from static low-speed signals to high-speed signals. The details of the present invention will be explained below based on the drawings.

FIG. 1 shows a conventional level adjuster in which a resistor and a transistor are connected in series, where 1 is a resistor, 2 is an enhanced field effect transistor, 3 is a power supply, and 4 is an input signal source. 5 is the output terminal of the level adjuster, but since the load capacitance of the next stage and the resistor 1 that follows this form an integrating circuit, reducing the value of the resistor 1 increases the power consumption, and increasing it increases the operating speed. Become.

FIG. 2 shows an embodiment of the level adjuster described in Patent Application No. 54539 of 1972, in which enhancement type field effect transistors 6 and 7 with different polarities are connected complementary to each other, and the source side of the transistors is connected in a complementary manner. voltages V _DD1 and X _SS1 are applied.

The gate electrode of the P channel type field effect transistor 6 and the gate electrode of the N channel type field effect transistor 7 are connected by a capacitor 8, the gate of the transistor 7 is connected to V _SS1 via a leakage diode 9, and the gate electrode of the transistor 6 is connected to the gate electrode of the transistor 6. is the input terminal, and the drains of the complementary transistors 6 and 7 are the output terminals. The input signal is high level is V _DD1 and low level is V _SS2
(V _DD1 > V _SS2 > V _SS1 ) The high level of the output signal is converted to V _DD1 and the low level is converted to V _SS1 .

However, since the charge in the capacitor 8 is discharged over time due to the leakage current of the leakage diode 9,
The range of use is limited to high-speed signals whose discharge time is negligible.

FIG. 3 is a block diagram in which the level adjuster of the present invention is used in a frequency dividing circuit.
1 operates with a 1.5V power supply 12, the frequency divider 14 is supplied with the power supply voltage of 6V from the booster circuit 13 or 3, and the level adjuster of the present invention is used to connect the signal from the frequency divider 11 to the frequency divider 14. 15 is inserted to convert the signal level.

FIG. 4 shows an embodiment of the voltage level adjuster of the present invention, in which 16 to 19 are P channel type field effect transistors, 20 to 23 are N channel type field effect transistors, 24 to 25 are capacitors, and 26 to 27 are N channel type field effect transistors. is composed of a leakage diode. Transistors 16, 18 and 17, 19 are connected in series, respectively, and the sources of transistors 16 and 17 are connected to power supply V _DD1 . The drains and sources of the transistors 20, 21 and 22, 23 are connected in parallel, the sources are connected to the power supply V _SS1 , the drains of the transistors 20, 21 are connected to the drain A of the transistor 18, and the drains of the transistors 22, 23 are connected to the transistor 19. It is connected to the drain B of.

Further, the gates of transistors 18 and 21 are connected to B
In addition, the gates of transistors 19 and 23 are connected to A. The gates of transistors 16 and 20 are connected through a capacitor 24, and the gates of transistors 17 and 22 are connected through a capacitor 25. The gate of transistor 20 is further connected to V _SS1 via a leakage diode, and similarly the gate of transistor 22 is connected to V _SS1 via a leakage diode 27. This level adjuster has two inputs, transistor 17
The gate line 29 of _the transistor 16 is the first input terminal, and the gate line 28 of the transistor 16 is the second input terminal.
There is an attached condition that the two input terminals (V _DD1 > V _SS2 > _{V SS1} ) at V SS2 do not become V _SS2 at the same time.

The output terminal 30 is taken out from point B, but if an opposite phase output is required, it may be output from point A. That is, the level adjuster of the present invention shown in FIG.
1, 19, and 23 are cross-connected to their respective gates and drains to form a flip-flop, which has a state storage function.

Also, transistors 16 and 17 are connected to V _DD1 and V _SS2
The transistors 20 and 22 are biased to V _SS1 by the leakage diodes 26 and 27, and the difference signal V _DD1 -V _DD2 of the input signal is superimposed on the previous bias via the capacitors 24 and 25. to switch each transistor. For slow signals, transistors 20 and 22
The gate signal of is differentiated due to the leakage diode, but the change in state that occurs when the input signal changes is stored in the flip-flop composed of transistors 18, 21 and 19, 23, and since the transistors are complementary connected, the output resistance It is characterized by extremely low current consumption in the binary output state.

FIG. 5 is an example of the operating waveform of the level adjuster shown in FIG. 4, and 31 is the first input terminal 29, 32.
is the input waveform of the second input terminal 28. High level is V _DD1 and low level is V _SS2 , so do not set V _SS2 to low level at the same time. 33 is the output signal, high level is V _DD1 , low level is V _SS1 , V _DD1 > V _SS2 > V _SS1
There is a relationship between

FIG. 6 shows the side when the two input terminals of the level adjuster according to the present invention are used as one input terminal,
34 is a level adjuster, 35 and 36 are first and second input terminals, and 37 is an output terminal.
The input terminal inverts the signal at the first input terminal with an inverter 38 to generate a signal at the second input terminal. The power supply of inverter 38 is the same as the input signal level
Let V _DD1 and V _SS2 .

FIG. 7 is an example of the operating waveform when used as one input terminal shown in FIG. 6, where 39 is the input waveform of high level V _DD1 and low level V _SS2 , and 40 is the input waveform of high level V _DD1 and low level V This is the output waveform of _SS2 .

Based on the above figures 3 to 7, the input signal
We have explained how to convert the V _SS2 level to V _SS1 (V _SS2 > V _SS1 ), but in the same way, the high level of the input signal is V _DD2 , the low level is V _SS1 , and the high level after level adjustment is V SS1 _DD1 and a voltage level adjuster whose low level is V _SS1 are shown in FIG.
(V _DD1 > V _SS2 > V _SS1 ) In other words, the voltage level adjuster shown in Fig. 4 is simply a configuration of P-channel and N-channel field effect transistors in phase axis, and therefore the position of the diode and input It is also in a symmetrical position to that in Figure 4.

41 to 44 are N channel type field effect transistors, 45 to 48 are P channel type field effect transistors, 49 to 50 are capacitors, and 51 to 48 are P channel type field effect transistors.
Reference numeral 52 denotes a leakage diode, and complementary connected transistors 43, 46 and 44, 48 have their gates and drains crossed, and transistor 41 in series with transistor 43.
and transistor 42 in series with transistor 44.
gates are the second and first input terminals 53 and 54, respectively.

Also, transistor 4 in parallel with transistor 46
5 and transistor 48 in parallel
7 are connected to input terminals 53 and 54 via capacitors 49 and 50, respectively.

Further, the gates of each of transistors 45 and 47 are connected to V _DD1 via leakage diodes 51 and 52. As is clear from the above explanation, the fourth
The voltage level adjuster of the present invention shown in FIG. 8 and _FIG.
Or, by inverting the configuration of the N-channel field effect transistor or P-channel type field effect transistor depending on V _SS1 and making the positions of the capacitor and diode relatively equivalent, a voltage level adjuster suitable for each purpose can be created. Can be done.

As described above, the voltage level adjuster of the present invention has a wide operating range from static operation to high-speed operation, and has a complementary configuration using P-channel and N-channel field effect transistors, so it consumes less power and has the advantage of being used in watches, etc. big.

In addition, in FIGS. 4 and 8, transistors 16, 18, 17, 19, and 41, 43 in series configuration
It goes without saying that even if the positions of and 42 and 43 are exchanged, their operations are exactly the same.

In addition, when integrating the present invention, it is necessary to separate the leakage diode, but the so-called SOS structure, in which silicone is produced on a sapphire substrate and each element is insulated and separated, has low stray capacitance and high speed. It has excellent properties and is easy to manufacture.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams of a conventional level adjuster, FIGS. 3 to 8 are circuit diagrams of an embodiment of the present invention, and FIG. 3 is a block diagram of a circuit using a level adjuster. 4 and 8 are circuit diagrams showing embodiments of the present invention, FIG. 5 is an operation waveform diagram explaining the operation of the circuit diagram in FIG. 4, and FIG. 6 is a simple diagram of the level adjuster in FIG. 4. This is a circuit diagram when using one input.
The figure is an operation waveform diagram of FIG. 6. 16, 17, 18, 19, 45, 46, 47,
48...P channel enhancement type field effect transistor, 20, 21, 22, 23, 41,
42, 43, 44...N-channel enhancement type field effect transistor, 26, 27, 51,
52...Diode, 24, 25, 49, 50...
...capacitor.

Claims (1)

[Scope of Claims] 1. In a voltage level adjuster used to connect circuits with different voltage levels, two complementary circuits are provided in which a P-channel type field effect transistor and an N-channel type field effect transistor are connected in a complementary manner, and each complementary circuit is A memory circuit is formed by connecting the gates of the circuits to the drains of transistors of other complementary circuits, and each N-channel transistor whose gate is grounded by a diode is connected in parallel with the N-channel transistor of the memory circuit, and the memory circuit A voltage level adjuster characterized in that a P-channel transistor is connected in series with a P-channel transistor, and the gates of the parallel and series transistors are each connected with a capacitor. 2. In a voltage level adjuster used to connect circuits with different voltage levels, two complementary circuits are provided in which a P channel type field effect transistor and an N channel type field effect transistor are connected in a complementary manner, and the gates of each complementary circuit are connected to each other. A memory circuit is formed by connecting the transistors to the drains of the complementary circuits, and each P-channel transistor whose gate is grounded by a diode is connected in parallel with the P-channel transistor of the memory circuit, and in series with the N-channel transistor of the memory circuit. A voltage level adjuster characterized by having a configuration in which an N-channel transistor is connected to each of the transistors, and the gates of the parallel and series transistors are each connected to a capacitor.