JPH02186826A - Level shifter - Google Patents

Abstract

PURPOSE:To increase an operating frequency without generating the weakening of a waveform in a signal by forming the subject device with a CMOS circuit without using a high resistor with high accuracy. CONSTITUTION:The gates and the drains of P-channel MOS transistors 1 and 2 whose sources are connected to a power source of 3V with a low potential system, respectively, are cross-connected, and furthermore, the drains of N- channel MOS transistors 3 and 4 whose sources are grounded are connected to respective drain. And high potential system signals A and the signals, the inverse of A with negative polarity are applied on the gates of the N-channel MOS transistors 3 and 4, and level shifted output i.e., the output of low potential level is taken out from the drain of the N-channel MOS transistor 4. Thus, since it is not required to form the high resistor with high accuracy in a CMOS semiconductor manufacturing process, the weakening in a signal waveform is hardly generated even when the operating frequency is increased while exceeding a certain level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a CMO3 logic circuit, and particularly to a level shifter that shifts the level of a signal supplied from a high potential system part to a low potential system part.

Conventional technology FIG. 3 shows an example of this type of level shifter.

In the figure, 11.12 is a level shift resistor, 5,
6 is an inverter, and 10 is a level shifter.

In this level shifter, when a signal is supplied from a high potential system part, for example, the output of inverter 5, to a low potential system part, for example, the input of inverter 6, the first. Second resistor 1
Level shifting is performed by 1.12.

That is, one end of the first resistor is connected to the output terminal of the inverter 5, the other end is connected to one end of the second resistor, and the second resistor is connected to the output terminal of the inverter 5.
The level shift function is achieved by the configuration in which the other end of the resistor is grounded and the input terminal of the inverter 6 is connected to the common connection point of the resistors 11 and 12.

FIG. 4 shows an operating waveform diagram when the high potential system is 5V and the low potential system is 3V.

Problems to be Solved by the Invention However, the above-mentioned bell shifter employing the resistance division method has the following problems to be solved. The first problem is that it is necessary to form a highly accurate high resistance using a CMO8 semiconductor process. The second problem is that the signal waveform becomes dull when the operating frequency exceeds a certain level.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention converts high-potential system signals into two-phase signals, and converts these signals into two N-channel MOSs provided in the low-potential system. It is used as the gate input of the transistor, and the two N-channel MO3) transistors are turned ON and OFF alternately.

When in the ON state, the P-channel MOS transistor is turned on so that a low potential level is output to the drain of the other N-channel MOS transistor.

Effect: According to this configuration, a resistor can be eliminated from the level shifter, and a level thick CMOS transistor configuration can be realized.

Example Embodiments of the present invention will be described using FIG. 1 and FIG. 2.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, and FIG. 2 is an operating waveform diagram thereof.

The level shifter of the present invention is a P-channel MOS transistor 1 whose sources are connected to a power supply (3V) in a low potential system.
, the gates and drains of 2 are cross-connected, and the source of each drain is grounded (N-channel MO3).
The drains of transistors 3 and 4 are connected and the N
High potential system signals A and A of opposite polarity are applied to the gates of channel MOS transistors 3 and 4, and a level shift output, that is, an output at a low potential level, is taken out from the drain of the N channel MOS transistor 4. .

In the level shifter configured in this way, when the signal A is at "Hi" level, the N-channel MOS transistor 3
The gate potential of N-channel MOS transistor 4 is OV.
Since the gate potential of is 5V, N-channel MOS transistor 3 is turned off, and N-channel MOS transistor 4 is turned off.
is turned on, and the drain of N-channel MOS transistor 4 becomes Ov. In this state, P channel MOS
The gate potential of transistor 1 becomes Ov, and P-channel MOS transistor 1 is turned on, so its drain becomes 3V, this voltage is applied to the gate of P-channel MOS transistor 2, and P-channel MO3) transistor 2 is turned off. Therefore, N-channel MO3) transistor 4 remains ON.

Next, when the signal A changes to the "LO" level, the gate potential of the N-channel MOS transistor 3 becomes 5V and turns ON, and the drain becomes Ov. On the other hand, N-channel MOS transistor 4 is turned off, but since the ON/OFF relationship of P-channel MO3 transistors 1 and 2 is also reversed, N-channel MOS transistor 4 is turned off.
It remains as it is. At this time, the drain of the N-channel MOS transistor 4, that is, the drain of the P-channel MOS transistor 2, is connected to the drain of the P-channel MOS transistor 2, which is turned on.
Therefore, it is the voltage (3V) of the power supply to which the source is connected.

Therefore, the signal B output from the inverter 6 is in phase with A, and the potential level is shifted from 5V to 3V.

As described in detail, the level shifter of the present invention can be realized with a CMO3 circuit without using high-precision high-resistance, so that signal waveform distortion does not occur and the operating frequency is improved. is played.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a level shifter according to the present invention, FIG. 2 is an operating waveform diagram, FIG. 3 is a circuit diagram of a conventional level shifter, and Figure 2 is an operating waveform diagram thereof. 1.2...P channel MOS transistor, 3
．． 4...N-channel MO8 transistor, 5°6.7...Inverter, 10...Level shifter, 11.12...Resistor. Figure Figure Figure Figure

Claims (1)

[Claims] The gates and drains of first and second P-channel MOS transistors each having a source connected to a power supply in a low potential system are cross-connected, and the first and second N-channel MOS transistors each have a drain and a source grounded. connecting the drains of the transistors, applying high potential two-phase signals of opposite polarity to the gate inputs of each of the N-channel MOS transistors;
A level shifter characterized in that a low potential signal is taken out from the drains of the N-channel and P-channel MOS transistors.