JPS6229929B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MOS logic circuit used, for example, in a master section and a slave section of a master-slave flip-flop.

An example of a conventional inverter circuit of this type is shown in FIG. In the figure, 1 and 2 are P channels
MOS transistors (hereinafter abbreviated as P MOS Tr), 3 and 4 are N-channel MOS transistors (hereinafter abbreviated as NMOS Tr), 5 and 6 are clock lines and inverted clock lines,
7 is an input terminal, and 8 is an output terminal. PMOS
Tr1 and NMOS Tr3 constitute a transmission gate, PMOS Tr2 and NMOS Tr4 constitute an inverter, and 9 is a connection point between these. FIG. 2 is an explanatory diagram of the operation of FIG. 1, and shows timing waveforms in the circuit of FIG. 1. In the figure, a and b are clock lines 5
and the voltage waveform of the inverted clock line 6, c is the voltage waveform of the input terminal 7, d is the voltage waveform of the connection point 9,
e shows the voltage waveform of the output terminal 8.
The third shows the input/output voltage transfer characteristics of the inverter. In the figure, NMOS Tr4 has cut-off characteristics in region A, saturation characteristics in regions B and C,
Regions D and E each exhibit triode characteristics, and P MOS
Tr2 exhibits cut-off characteristics in region E, saturation characteristics in regions C and D, and triode characteristics in regions A and B, respectively.

Next, the operation of the inverter circuit shown in FIG. 1 will be explained with reference to FIGS. 2 and 3.

The initial voltage is high voltage at input terminal 7, and high voltage at connection point 9.
Consider the case where the output terminal 8 is a low voltage and the output terminal 8 is a high voltage. When the clock line 5 is at a high voltage and the inverted clock line 6 is at a low voltage, the voltage at the input terminal 7 is not read, and the voltage at the connection point 9 and the output terminal 8 is
retains the previous state.

Next, when the clock line 5 changes to low voltage and the inverted clock line 6 changes to high voltage, P
MOS Tr1 and NMOS Tr3 are turned on, and the voltage at input terminal 7 is first transmitted to connection point 9. The voltage at the node 9 changes from a low voltage to a high voltage, as shown in FIG. 2d. Areas B and C in Figure 3
In, P MOS Tr2 and N MOS Tr
4 are both in the on state, and the voltage at the output terminal 8 is P
It decreases depending on the division ratio of the on-resistances of MOS Tr2 and NMOS Tr4, but does not reverse. Area D,
At E, the voltage at node 9 exceeds the inverter's transition voltage (usually about 1/2 of the supply voltage VDD) and the output terminal 8 inverts to a low voltage.

Although not shown, input terminal 7 is used as the initial voltage.
The same explanation can be given for the case where is a low voltage, connection point 9 is a high voltage, and output terminal 8 is a low voltage.

As mentioned above, in the conventional circuit, the transition voltage of the inverter is as large as approximately VDD/2, so the saturation region is wide, and moreover, during the transition period, the PMOS
Both Tr2 and NMOS Tr4 are in the on state, and one MOS Tr enters the triode region and P
After obtaining the division ratio of the on-resistances of MOS Tr2 and NMOS Tr4, the output voltage is inverted. Therefore, the rise and fall times are long, and in the example shown with the symbol T in Figure 2e, when VDD = 5V, the 10% to 90% value is approximately
It is 10ns.

In view of the above points, the present invention has been made to solve such problems.The purpose of the present invention is to turn off both MOS transistors of the not gate, which is the output stage circuit of the inverter, when reading input information. The object of the present invention is to provide a complementary MOS logic circuit in which the transition voltage value is reduced and the output rise and fall times are shortened by turning on only one MOS Tr.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a circuit diagram showing an embodiment of a complementary MOS logic circuit according to the present invention. In FIG. 4, the same reference numerals as in FIG. 1 indicate corresponding parts, 10,
11 and 12 are P MOS Tr, and 13, 14 and 15 are N MOS Tr. PMOS Tr1
The source electrodes of 0 and 11 are connected to the power supply VDD,
The source electrodes of the NMOS Tr14 and 15 are grounded. The drain electrode of P MOS Tr10 is N
Drain electrode of MOS Tr13 and PMOS Tr11
This connection point is referred to as a terminal 16. P MOS Tr10 and N MOS
The gate electrode of Tr13 is connected to the inverting clock line 6. The drain electrode of N MOS Tr14 is connected to the drain electrode of P MOS Tr12.
It is connected to the gate electrode of MOS Tr15,
This connection point is designated as terminal 17. NMOS Tr14
The gate electrodes of the PMOS Tr 12 and PMOS Tr 12 are connected to the clock line 5. N MOS Tr13 and P
The respective source electrodes of the MOS Tr 12 are commonly connected, and this connection point is defined as an input terminal 7. PMOS
The respective drain electrodes of Tr11 and NMOS Tr15 are commonly connected, and this connection point is defined as output terminal 8.

FIG. 5 is an explanatory diagram of the operation of FIG. 4, and shows timing waveforms in the embodiment of FIG. 4. In the figure, a and b are the voltage waveforms of the clock line 5 and the inverted clock line 6, c is the voltage waveform of the input terminal 7, d is the voltage waveform of the terminal 16, e is the voltage waveform of the terminal 17, and f is the voltage waveform of the output terminal 8. This shows the voltage waveform.

Figure 6 shows P MOS Tr11 and N MOS Tr15.
This figure shows the input/output voltage transfer characteristics of a circuit (hereinafter abbreviated as a not gate) composed of the following.
In the figure, N MOS Tr15 has cut-off characteristics in region F, saturation characteristics in region G, and triode characteristics in regions H, I, and J, while P MOS Tr11 has cut-off characteristics in region J, saturation characteristics in region I, and Regions F, G, and H each show triode characteristics.

Next, the operation of the embodiment shown in FIG. 4 will be explained with reference to FIGS. 5 and 6. As for the initial voltage, consider the case where input terminal 7, terminals 16 and 17, and output terminal 8 are all at high voltage. When the clock line 5 becomes a high voltage and the inverted clock line 6 becomes a low voltage, PMOS Tr10 and NMOS Tr14 are turned on, and NMOS Tr13 and PMOS Tr12 are turned off. As a result, the voltage at the input terminal 7 is not read, the terminal 16 becomes a high voltage, and the terminal 17 becomes a low voltage. At this time, the voltage at the terminal 17 changes from a high voltage to a low voltage as shown in FIG. 5e. Therefore, both PMOS Tr11 and NMOS Tr15 are in the off state, and the output terminal 8 maintains its previous state.

Next, when the clock line 5 changes to low voltage and the inverted clock line 6 changes to high voltage, P
MOS Tr10 and N MOS Tr14 are turned off, and N
MOS Tr13 and P MOS Tr12 are turned on. At this time, the voltage at input terminal 7 is transmitted to each terminal 16, 17. Since the input terminal 7 is at a high voltage, the voltage at the terminal 17 changes from a low voltage to a high voltage as shown in FIG. 5e, and the voltage at the terminal 16 remains at a high voltage. Therefore, P MOS Tr11
remains off, and only NMOS Tr15 is turned on. As can be seen from FIG. 6, the transition voltage at the not gate is approximately equal to the threshold voltage VIN of the NMOS Tr 15, and the saturation region is narrow. N
When MOS Tr15 enters the triode region, output terminal 8
is inverted from a high voltage to a low voltage, as indicated by the symbol T' in FIG. 5f, and the information at the input terminal 7 is transmitted.

Although not shown, the same explanation can be given when the input terminal 7 is a low voltage and the output terminal 8 is a high voltage as an initial voltage. At this time, P MOS Tr1
Only 1 is turned on, and the transition voltage of the not gate is
VDD-P MOS Tr11 threshold voltage | VTP
It becomes almost equal to |.

As is clear from the above, the circuit of this embodiment described above uses the clock line 5 and the inverted clock line 6 to
By turning on MOS Tr10 and N MOS Tr14, the not gate P MOS Tr11
and N MOS Tr 15 are turned off, and only one MOS Tr is turned on during reading.
Therefore, compared to the conventional circuit, the transition voltage value at the not gate becomes smaller, one MOS Tr starts operating in the triode region earlier, and the P MOS Tr11 and N MOS Tr15 at the not gate
Since the division ratio of the on-resistance is independent of the inversion of the output voltage, the rise and fall times are shortened. For example, when VDD=5V, the rise time is about 10 ns in the conventional circuit shown in FIG. 5ns, which is faster than conventional circuits.

As explained above, the complementary form according to the present invention
According to the MOS logic circuit, both of the not gates, which are the output stage circuits of the inverter, are
MOS Tr is turned off and one of them is turned off during reading.
Since only the MOS Tr is turned on, the transition voltage can be reduced compared to conventional circuits of this type, and the rise and fall times can be shortened to increase speed, making it possible to operate the circuit with a high-speed clock of 50MHz or higher. It has great practical effects in terms of implementation.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional complementary MOS logic circuit, Figure 2 is its operating waveform diagram, Figure 3 is an input/output voltage transfer characteristic diagram of the inverter section in Figure 1,
FIG. 4 is a circuit diagram showing an embodiment of the present invention, FIG. 5 is an operating waveform diagram thereof, and FIG. 6 is a diagram of input/output voltage transfer characteristics of the not gate shown in FIG. 4. In the figure, 5 is a clock line, 6 is an inverted clock line, 7 is an input terminal, 8 is an output terminal, 1
0 to 12 are P-channel MOS transistors, and 13 to 15 are N-channel MOS transistors.
It is a transistor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1 a first complementary MOS transistor circuit connected between an input terminal and a first level potential source, with a common gate terminal connected to a clock line; a second complementary MOS transistor circuit connected to each other and having a common gate terminal connected to the inverting clock line; a third complementary MOS transistor circuit connected between the first level potential source and the second level potential source; The output of the first complementary MOS transistor circuit is applied to one gate of a pair of MOS transistors constituting the third complementary MOS transistor circuit, and the output of the first complementary MOS transistor circuit is applied to the other gate of the pair of MOS transistors constituting the third complementary MOS transistor circuit. A complementary MOS logic circuit, characterized in that an output of a complementary MOS transistor circuit is applied thereto, and a common drain terminal of the third complementary MOS transistor circuit is used as an output terminal.