JPS55656A - Complementary mos logic circuit - Google Patents

Complementary mos logic circuit

Info

Publication number
JPS55656A
JPS55656A JP7357878A JP7357878A JPS55656A JP S55656 A JPS55656 A JP S55656A JP 7357878 A JP7357878 A JP 7357878A JP 7357878 A JP7357878 A JP 7357878A JP S55656 A JPS55656 A JP S55656A
Authority
JP
Japan
Prior art keywords
complementary mos
circuits
terminal
output
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7357878A
Other languages
Japanese (ja)
Other versions
JPS6229929B2 (en
Inventor
Toshiyuki Araki
Takeshi Tokuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7357878A priority Critical patent/JPS55656A/en
Publication of JPS55656A publication Critical patent/JPS55656A/en
Publication of JPS6229929B2 publication Critical patent/JPS6229929B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To minimize the transition voltage value as well as to reduce the rise and fall time of the output for the complementary MOS logic circuit which is used at the master and slave parts of the master/slave flip-flop. CONSTITUTION:First complementary MOS transistor circuits 12 and 14 whose common gate terminal is connected to clock line 5 are connected between input terminal 7 and the first-level potential source (earth). And second complementary MOS transistor circuits 10 and 13 whose common gate terminal is connected to clock line 6 are connected between terminal 7 and second-level potential source VDD. Furthermore, output 17 of circuits 12 and 14 is applied to one gate of thrid complementary MOS transistor circuits 11 and 15, and output 16 of circuits 10 and 13 is applied to the other gate respectively. And the common drain terminal of circuits 11 and 15 is used as output terminal 8.
JP7357878A 1978-06-16 1978-06-16 Complementary mos logic circuit Granted JPS55656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7357878A JPS55656A (en) 1978-06-16 1978-06-16 Complementary mos logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7357878A JPS55656A (en) 1978-06-16 1978-06-16 Complementary mos logic circuit

Publications (2)

Publication Number Publication Date
JPS55656A true JPS55656A (en) 1980-01-07
JPS6229929B2 JPS6229929B2 (en) 1987-06-29

Family

ID=13522307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7357878A Granted JPS55656A (en) 1978-06-16 1978-06-16 Complementary mos logic circuit

Country Status (1)

Country Link
JP (1) JPS55656A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56171589U (en) * 1980-05-23 1981-12-18
DE3311025A1 (en) 1982-03-26 1983-10-20 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa LOGIC CIRCUIT WITH THREE OUTPUT LEVELS
US4686396A (en) * 1985-08-26 1987-08-11 Xerox Corporation Minimum delay high speed bus driver

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56171589U (en) * 1980-05-23 1981-12-18
DE3311025A1 (en) 1982-03-26 1983-10-20 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa LOGIC CIRCUIT WITH THREE OUTPUT LEVELS
US4491749A (en) * 1982-03-26 1985-01-01 Tokyo Shibaura Denki Kabushiki Kaisha Three-output level logic circuit
US4686396A (en) * 1985-08-26 1987-08-11 Xerox Corporation Minimum delay high speed bus driver

Also Published As

Publication number Publication date
JPS6229929B2 (en) 1987-06-29

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