JPH01161913A - Clock driver circuit - Google Patents

Abstract

PURPOSE:To generate a clock signal whose leading and trailing speed is always constant by providing a constant current source circuit between a 1st MOS switch and a 1st potential or between a 2nd MOS switch and a 2nd potential. CONSTITUTION:With a changeover of an input signal In from '0' level to '1' level or from '1' level to '0' level conversely, when an N-channel MOS transistor(TR) 4 or a P-channel MOS TR 2 changes from the OFF state to the ON state, a parasitic capacitor 5 is charged or discharged by a constant current from a constant current source circuit 1(3). The leading speed of an output signal (out) depends on the current of the constant current source circuit 1 and the trailing speed of the output signal (out) depends on the current of the constant current source circuit 3. Thus, both the currents are always made constant and the leading and trailing speed is always made constant.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a clock driver circuit that amplifies an input clock signal.

(Prior art) Sample and hold circuits and switched capacitor filter circuits (Switched Capacitor F
(hereinafter referred to as SCF) etc., analog signal voltage is sampled through a switching element such as a MOS switch and stored in a capacitor, and a clock signal is used to control the switching element. . Normally, the switching elements in a CMO3 circuit are a P-channel MOS) transistor and an N-channel MOS transistor.
S) transistors are used, and complementary lock signals φ and φ are used as clock signals to control both transistors.

FIG. 8(a) is a circuit diagram showing the configuration of a clock driver circuit that generates the complementary lock signals φ and φ. The input clock signal φ is input via an inverter 31 to an inverter 32 as a driver for the clock φ, and also to an inverter 33 as a driver for the clock φ. As shown in the circuit diagram of FIG. 8(b), the inverter 32 or 33 has a voltage between the source and the drain between the power supply potential VCC and the ground potential VS.
A P-channel MOS transistor 34 and N
A clock signal φ or an output signal Out as φ is outputted from a common drain of both transistors 34 and 35.

FIG. 9 is a circuit diagram showing the configuration of a sample and hold circuit controlled by clock signals φ and φ output from the clock driver circuit of FIG. 8(a). The analog signal voltage Vin is applied to a CMO transistor composed of an N-channel MOS transistor 36 and a P-channel MOS transistor 37.
The voltage is stored in a capacitor 39 via an S analog switch 38 and output as a voltage V out. Note that the capacitors ff1Cp1Cp' in the figure represent the N channel and P channel M constituting the analog switch 38, respectively.
This is an equivalent representation of the parasitic capacitance, wiring capacitance, etc. of the OS transistors 36 and 37.

In such a configuration, the parasitic capacitance fA Cp sC
When variations occur in p/, the power supply potential vCc, or the threshold voltages of the transistors 34 and 35, variations occur in the rising and falling speeds of the clock signals φ and φ output from the clock driver circuit. For example, power supply potential VC
When variations occur in C, the clock signal φ exhibits various rising and falling speeds as shown in the waveform diagram of FIG.

By the way, it is known that an offset voltage occurs in the output voltage Vout in a sample Q-hold circuit as shown in FIG. 9. If there are variations in the rising and falling speeds of the clock signals φ and T, variations occur in this offset voltage.
ID-STATECIRCUITS, VOL, 5C-
19, No.

4, AUGUST, 1984J, etc.

According to this document, as shown in the waveform diagram of FIG. 11, when the sampling switch in the sample-and-hold circuit is turned off, the clock signal φ leaks through the parasitic capacitance, which causes an offset voltage to be applied to the output voltage V out. It is said that the value increases as the clock signal falls or rises faster.

As described above, variations in the offset voltage due to variations in the rising and falling speeds of the clock signal cause variations in circuit characteristics of sample-and-hold circuits, SCFs, and the like.

(Problems to be Solved by the Invention) As described above, in the conventional clock driver circuit, a change occurs in the rising or falling speed of the clock signal. Therefore, the offset voltage changes in the sample-and-hold circuit, SCF, etc., and there is a problem in the stability of the characteristics.

The present invention has been made in consideration of the above-mentioned circumstances, and its object is to provide a clock driver circuit that generates a lock signal whose rising and falling speeds are always constant.

[Structure of the Invention] (Means for Solving the Problems) The clock driver circuit of the present invention includes a first circuit that is inserted between a first potential and an output terminal of a clock signal, and whose conduction is controlled based on an input clock signal. 1 conductivity type first MOS
a second MOS switch of a second conductivity type inserted between a second potential and the output terminal and whose conduction is controlled based on an input clock signal;
between the OS switch and the first potential or the second potential.
and a constant current source circuit inserted between the MOS switch and the second potential.

(Function) Charges and discharges the clock signal output terminal with a constant current. This prevents changes in the rising or falling speed of the output signal due to the power supply voltage, the threshold value of the MOS transistor, or the like.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first block driver circuit according to the present invention.
1 is a circuit diagram showing a configuration according to an embodiment of the invention, or specifically shows a song. One end of the constant current source circuit 1 is connected to the power supply potential VCC. The other end of constant current source circuit 1 is connected to the source of P channel MOS transistor 2.

Furthermore, one end of the constant current source circuit 3 is connected to the ground potential VSS. The source of an N-channel MOS transistor 4 is connected to the other end of the constant current source circuit 3. The gates of both transistors 2.4 are commonly connected, and the input signal In is input to this common gate. Furthermore, the drains of both transistors 2.4 are commonly connected, and the clock signal φ or the signal Out as φ is outputted from this common drain. In addition, the common drain and the ground potential vss
A parasitic capacitor fi15 is connected between.

In the circuit having the above configuration, the input signal In is switched from the "0" level to the 1" level, or conversely from the "1" level to the "0" level, and the input signal In is switched from the "1" level to the "0" level (N-channel MOS).
transistor 4 or P channel MOS) transistor 2
changes from off state to on state, constant current source circuit 1
Alternatively, the parasitic capacitance 5 is charged or discharged by the constant current 3. Here, the rising speed of the output signal out is determined by the current value of the constant current source circuit 1, and the falling speed of the output signal out is determined by the current value of the constant current source circuit 3. As a result, since both type current values are always kept constant, the rising and falling speeds of the output signal Out can always be kept constant.

Therefore, when the output signal obtained by the above-described embodiment circuit is supplied as a clock signal to a sample-and-hold circuit, an SCF, etc., variations in circuit characteristics such as offset voltage can be prevented.

FIG. 2 shows the constant current source circuit 1 in the first embodiment circuit.
．． FIG. 3 is a circuit diagram showing a specific configuration when 3 is realized by a current mirror circuit. One constant current source circuit 3 includes two N-channel MOS transistors 6 whose gates are commonly connected.
．． 7 and a constant current source 9.

Transistor 6 is an input side transistor of current mirror circuit 8, and receives a constant current from constant current source 9. Transistor 7 is an output side transistor of current mirror circuit 8, and its source and drain are inserted between the source of transistor 4 and ground potential VSS. Here, if the element sizes of both transistors 5.7 are made equal, a constant current having a value equal to that of the constant current source 8 can flow through the transistor 7.

The other constant current source circuit 1 includes an N-channel MOS transistor 10 whose gate is commonly connected to the transistor 6, and two P-channel MOS transistors whose gates are commonly connected to each other.
It consists of two current mirror circuits 13 and 14 made up of S transistors 11 and 12, and the drains of the transistors 11 and 12 are connected to the power supply potential VCC. Transistor 6 is an input side transistor of one current mirror circuit 13, and receives a constant current from constant current source 9. Transistor 10 is an output side transistor of one current mirror circuit 13. The transistor 12 is an input terminal transistor of the other current mirror circuit 14, and the transistor 12 is the input end transistor of the other current mirror circuit 14, and the transistor 12 is the input end transistor of the other current mirror circuit 14, and
3 output current is input. The transistor 11 is the output side transistor of the other current mirror circuit 14,
The source and drain thereof are inserted between the source of the transistor 2 and the power supply potential VCC. Here, if the element sizes of the transistors 6 and IO and the transistors 11 and 12 are made equal, a constant current having a value equal to that of the constant current source 9 can flow through the transistor 11.

FIGS. 3 and 4 are circuit diagrams showing structures according to second and third embodiments of the invention, respectively. In the first embodiment circuit, two constant current source circuits 1.3 are provided to charge and discharge the capacitor 5, and the rise and fall speeds of the output signal Out are made constant. However, the sample
Offset voltage in hold circuits and the like occurs only when the switch is turned off. Therefore, it is only necessary to keep the speed at which the switch is turned off constant. Here, in order to keep the speed at which the switch turns off constant when the sampling switch is composed of only N-channel MOS transistors, it is necessary to use a capacitor as shown in the embodiment circuit of FIG. ! Only one constant current source circuit 3 may be provided so that the current value during discharge of i15 is constant.

On the other hand, in order to keep the switching speed constant when the sampling switch is composed of only P-channel MOS transistors, as shown in the embodiment circuit of FIG. It is sufficient to provide only the other constant current source circuit 1 so that the current value during charging is constant.

FIG. 5 is a circuit diagram showing a configuration according to a fourth embodiment of the present invention. In this embodiment circuit, each constant current source circuit 1.3 has the switching function of the transistor 2.4 in the embodiment circuit shown in FIG.

One of the constant current source circuits 15 used in place of the constant current source circuit 3 includes an N-channel MOS transistor 1B as an output side transistor, and an N-channel MOS transistor 17.
a current mirror circuit 18 having as an input transistor,
A constant current source 19 that supplies a constant current to the transistor 17 and two N-channel MOS transistors 2 for switching.
0.21 is provided. One N for the above switch
The channel MOS) transistor 20 is inserted between the gates of the transistors 1B and 17 constituting the current mirror circuit 18, and the input signal In is supplied to the gate. The other N-channel MOS transistor 21 for switching is connected to the gate of the transistor 16 and the ground potential vS.
S, and the input signal I is inserted into its gate.
n inverted signals In are supplied.

The other constant current source circuit 22 used in place of the constant current source circuit 1 includes a P channel MOS transistor 23 as an output side transistor, and a P channel MOS transistor 24.
a current mirror circuit 25 having as an input side transistor,
A constant current source 2B that supplies a constant current to the transistor 24 and two P-channel MOS transistors 2 for switching
7.28 is provided. One P for the above switch
The channel MOS transistor 27 is inserted between the gates of transistors 23 and 24 constituting the current mirror circuit 25, and the input signal In is supplied to the gate thereof. The other P-channel MOS transistor 28 for switching is connected to the gate of the transistor 23 and the power supply potentials v, s.
is inserted between the input signal In and the gate of the input signal In
An inverted signal In is supplied.

In a circuit with such a configuration, when the input signal In is “0”
When switching from level to level 10, constant current source circuit 1
Transistor 20 in 5 is on, transistor 21
is turned off, and the current mirror circuit 18 becomes operational. At this time, the parasitic capacitance ff15 is discharged by the constant current flowing through the transistor 16.

On the other hand, when the input signal In switches from the "1" level to the "0" level, the transistor 27 in the constant current source circuit 22 is turned on, the transistor 28 is turned off, and the current mirror circuit 25 is now operable. become. At this time, the parasitic capacitance 5 is charged with a constant current flowing through the transistor 23.

Therefore, also in the case of this embodiment circuit, the rising and falling speeds of the output signal Out can always be kept constant.

FIGS. 6 and 7 are circuit diagrams showing configurations according to fifth and sixth embodiments of the present invention. The fifth and sixth embodiment circuits are designed to keep either the rising or falling speed of the output signal Out constant, as in the case of the embodiment circuits of FIGS. 3 and 4. be.

In the case of the embodiment circuit shown in FIG. 6, the constant current source circuit 15 is left in place to keep the falling speed of the output signal Out constant, and the switch is controlled by the signal In to charge the parasitic capacitance 5. A P channel MOS transistor 29 is provided.

In the case of the embodiment circuit shown in FIG. 7, the constant current source circuit 22 is left in place to keep the rising speed of the output signal Out constant, and the N switch is controlled by the signal In to discharge the parasitic capacitance 5. A channel MOS transistor 30 is provided.

Note that the condition for each of the constant current sources 9, 19, and 2B is that the power supply potential is V. It is necessary that the value does not change even if 0 changes, and as a device that satisfies this condition, for example, the device described in Japanese Patent Publication No. 56-2017 can be used.

With the above configuration, the influence on the characteristics of the SCF, sample-and-hold circuit, etc. can be significantly reduced.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a clock driver circuit in which a lock signal can be obtained by rising and falling at a constant rate without affecting the power supply voltage or the threshold value of an element, etc. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration according to a first embodiment of the invention, FIG. 2 is a circuit diagram showing a specific configuration of the circuit in FIG. 1, and FIG. 3 is a configuration according to a second embodiment of the invention. 4 is a circuit diagram showing a configuration according to a third embodiment of the invention, FIG. 5 is a circuit diagram showing a configuration according to a fourth embodiment of the invention, and FIG. 6 is a circuit diagram showing a configuration according to a fourth embodiment of the invention. A circuit diagram showing the configuration according to the fifth embodiment, FIG. 7 is a circuit diagram showing the specific configuration of the circuit of the sixth embodiment, and FIG. 8 shows the entire and partial configuration of a conventional clock driver circuit. FIG. 9 is a circuit diagram showing the configuration of a sample-and-hold circuit, FIG. 10 is a waveform diagram of a clock signal, and FIG. 11 is a waveform diagram of a clock signal waveform and an offset voltage thereof. 1.3... Constant current source circuit, 2... P channel MOS
Transistor, 4...N channel MOS transistor, 5... Parasitic capacitance. Applicant's representative Patent attorney Takehiko Suzue No. 1 Account No. 20 m30 No. 40 FA60 No. 7F7I

Claims (3)

[Claims] (1) A first electrode that is inserted between the first potential and the output terminal of the clock signal and whose conduction is controlled based on the input clock signal.
a first MOS switch of a conductivity type; a second MOS switch of a second conductivity type inserted between a second potential and the output terminal and whose conduction is controlled based on an input clock signal; A clock driver circuit comprising: a constant current source circuit inserted between the MOS switch and the first potential or between the second MOS switch and the second potential. (2) The constant current source circuit includes a current mirror circuit composed of MOS transistors on the input side and output side whose gates are commonly connected, and a constant current source that supplies a constant current to the MOS transistor on the input side. Claim 1 characterized in that
The clock driver circuit described in section. (3) The clock driver circuit according to claim 1, wherein the constant current source circuit also functions as the first MOS switch or the second MOS switch.