JPS60117910A - Comparator - Google Patents
ComparatorInfo
- Publication number
- JPS60117910A JPS60117910A JP58225819A JP22581983A JPS60117910A JP S60117910 A JPS60117910 A JP S60117910A JP 58225819 A JP58225819 A JP 58225819A JP 22581983 A JP22581983 A JP 22581983A JP S60117910 A JPS60117910 A JP S60117910A
- Authority
- JP
- Japan
- Prior art keywords
- output
- type
- comparator
- potential
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
Abstract
Description
【発明の詳細な説明】
不発明はトランジスタ、特に電界効果トランジスタ（以
下、ＦＥＴという）を用いた比較回路に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The invention relates to a comparison circuit using transistors, particularly field effect transistors (hereinafter referred to as FETs).
第１図は従来、良く知られた比較回路の一例である・第
１図において、６および７はＰ形ＦＥＴで８および９は
Ｎ形ＦＥＴであシ、ｌＯの電流源とともに、人力２と入
力３を比較する比較回路を構成している。Ｎ形ｊ’ＥＴ
１１と定電流＃１２は。Figure 1 is an example of a conventionally well-known comparison circuit. In Figure 1, 6 and 7 are P-type FETs, 8 and 9 are N-type FETs, and with a current source of 1O, It constitutes a comparison circuit that compares input 3. N type j'ET
11 and constant current #12.
は、比較回路の出力振幅ｒ端子ｌ又は端子４に供給され
る電蝕電圧程度の振幅まで変換する田方回路を構成し、
端子５から出力が得られる・以下、同図の回路の動作を
説明する。まず、入力端子２の電位が入力端子３の電位
よシ高い場合。constitutes a Tagata circuit that converts the output amplitude of the comparison circuit r to an amplitude approximately equal to the galvanic voltage supplied to terminal l or terminal 4,
Output is obtained from terminal 5.The operation of the circuit shown in the figure will be explained below. First, when the potential of input terminal 2 is higher than the potential of input terminal 3.
Ｎ型ＦＥＴ８は専迫し、Ｎ型ＦＥＴ９は遮断している。N-type FET 8 is dedicated and N-type FET 9 is cut off.
この結果２足電流源１０の電流ｅｉＮ型Ｆ Ｅ Ｔ ８
→Ｐ型に’ Ｅ Ｔ ６→電源端子１の径路で流れる。As a result, the current of the two-leg current source 10 is eiN type F E T 8
→P-type 'ET 6→Flows through the path of power terminal 1.
このとき、Ｐ型に’ＢＴ６のゲートには、これｋＲれる
電流による電圧降下が生じてお９、この電圧はＰ型ＦＥ
Ｔ７のゲートにも接続されているため、Ｐ型ＦＥＴ７も
導通状態となる。前述の如（、Ｎ型ｆｉ’ＥＴ９は遮断
しているため、Ｐ型にＥＴＩＩのゲートには電源端子１
の電位が印加され、Ｐ型ＦＥＴＩＩは遮断状態にある。At this time, a voltage drop occurs at the gate of P-type 'BT6 due to the current flowing through this kR, and this voltage is
Since it is also connected to the gate of T7, P-type FET7 also becomes conductive. As mentioned above (because N-type fi'ET9 is cut off, power supply terminal 1 is connected to the gate of P-type ETII).
is applied, and the P-type FET II is in a cutoff state.
出力の寄生負荷容蓋１３は、この結果。The output parasitic load capacitor 13 is the result of this.
定電流源１２によ多出力端子５が電源端子４と同電位と
なるまで放電される。The constant current source 12 discharges the output terminal 5 until it reaches the same potential as the power supply terminal 4.
次に、入力端子２の電位が入力端子３の電位よシ低くな
った場合、今夏はＮ型ＦＥＴ８は遮断、Ｎ型ＦＥＴ９は
導通する。Ｎ型ＦＥＴ８が遮断するため。Next, when the potential of the input terminal 2 becomes lower than the potential of the input terminal 3, the N-type FET 8 is cut off and the N-type FET 9 is made conductive this summer. Because N-type FET8 shuts off.
Ｐ型）’ＥＴ６に電流が流れなくなシ、七のゲート電位
は電源端子ｌに近づく、よって、Ｐ５ＦＥＴ７も遮断す
ることになる。このとき、前述の如（、Ｎ型ＦＥＴ９は
４通しているので、定電流１ｏの電流は、Ｎ型ＦＥＴ９
→Ｐ型ＦＥＴＩＩゲートの径路で流れ、Ｐ型ｆｉ’ＥＴ
１１ のゲート電位を低下させて４辿δせる。一般に、
Ｐ型ＦＥＴＩＩ の電流供給能力は定電流源１２のそれ
よシ光分大きいので、出力の負荷容量１３はＰ型ＦＥＴ
ＩＩ によシ充電され、出力電圧５は電源端子１に近い
電位となる。When current no longer flows through P-type FET6, the gate potential of FET7 approaches the power supply terminal l, and P5FET7 is also cut off. At this time, as mentioned above (since 4 N-type FETs 9 are passed through, the current of constant current 1o is
→Flows in the path of P-type FET II gate, P-type fi'ET
By lowering the gate potential of 11, 4 traces δ can be obtained. in general,
The current supply capacity of P-type FET II is larger than that of constant current source 12 by an amount of light, so the output load capacitance 13 is
II, the output voltage 5 becomes a potential close to that of the power supply terminal 1.
以上に述べたようにして、従来の回路では入力端子２と
入力端子３の電位の比較を行っているが、前述の説明か
ら、従来の回路において、出力の整定時間を決定するの
は、出力の立下が多時には定電流源１２リドライブ能力
であシ、立上が少時は定電流＃１２とＰｍＦＥＴ１１の
ドライブ能力の差であることがわかる。従って、短い整
定時間が要求される場合には、定電流源１２とＰｉＪＦ
ＢＴｌｌに大きなドライブ能力を持たせねばならないが
。As described above, in the conventional circuit, the potentials of input terminal 2 and input terminal 3 are compared, but from the above explanation, in the conventional circuit, the settling time of the output is determined by the output It can be seen that when there are many falls, it is due to the redrive ability of the constant current source 12, and when there are few rises, it is due to the difference in the drive ability of the constant current #12 and the PmFET 11. Therefore, if a short settling time is required, the constant current source 12 and the PiJF
BTll must have a large drive ability.
その場合１回路の消費電流が増大して好ましくなかった
。In this case, the current consumption of one circuit increases, which is not desirable.
不発明の目的は消費電流をおさえて出力の整定時間を短
くした比較回路を提供することにある。An object of the invention is to provide a comparator circuit that reduces current consumption and shortens output settling time.
不発明は、二つの比較器を用い、一方の出力で他方を、
他方の出力で一方をそれぞれ制御するようにしたことを
特徴とし、以下に１囲を用いて本発明を詳述する。The invention uses two comparators, with the output of one outputting the other,
The present invention is characterized in that one is controlled by the output of the other, and the present invention will be described in detail using the following paragraphs.
第２図は、本発明の一実施例である。第２図において、
８．９はＮ型ＦＥＴ、６．７はＰ型ＦＥＴであシ、Ｎ型
ＦＥ’ｌ’１４ と定電流源ｌＯとともに第１の比較器
２１を構成する。１７．１８はＰ型ＦＥＴ。FIG. 2 is an embodiment of the present invention. In Figure 2,
8.9 is an N-type FET, and 6.7 is a P-type FET, which constitute the first comparator 21 together with the N-type FE'l'14 and the constant current source IO. 17.18 is a P-type FET.
１９．２０はＮ型ＦＥＴであシ、Ｐ型ＦＥＴ１６．足電
流源１５とともに第２の比較器２２を構成する。19.20 is an N-type FET, and P-type FET16. A second comparator 22 is configured together with the foot current source 15.
１．４は電源端子、２．３は入力端子で５は出力端子で
ある。1.4 is a power supply terminal, 2.3 is an input terminal, and 5 is an output terminal.
以上のように構成された第２図の回路の動作を以下に説
明する。まず、入力端子２の電位が入力端子３の電位よ
り高い場合、Ｎ型ＦＥＴ８が導通。The operation of the circuit of FIG. 2 constructed as above will be explained below. First, when the potential of input terminal 2 is higher than the potential of input terminal 3, N-type FET 8 becomes conductive.
Ｎ型）”ＥＴ９が遮断であシ、Ｐ型ＦＥｉ’６．７は導
通となって出力５には電源端子１の電位が現れる。N-type) ET9 is cut off, P-type FEi'6.7 becomes conductive, and the potential of power supply terminal 1 appears at output 5.
このと′Ｉ！！、％Ｐ型ＦＥＴ１６のゲートには出力５
と同じ電位が印加されているため％ＰＰｍＦＥＴ１１は
遮断状態にあシ、この結果、比較器２２は動作せず、比
較器２２の出力はフローティングになっている。This and 'I! ! , %The gate of P-type FET16 has output 5.
Since the same potential is applied, the %PPmFET 11 is in a cutoff state, and as a result, the comparator 22 does not operate, and the output of the comparator 22 is floating.
Ｎ型ＦＥＴ１４のゲートには電源端子ｌの電位がかかっ
ているので、ＦＥＴ１４は十分深く導通しており１足電
流源１０のインピーダンスをよシ高いものとしている。Since the potential of the power supply terminal l is applied to the gate of the N-type FET 14, the FET 14 is sufficiently deeply conductive and the impedance of the single current source 10 is made higher.
次に、入力端子２の電位が入力端子３の電位よシ低くな
るとＮ型ＦＥＴ８が遮断、Ｎ型ＦＥＴ９が導通し、Ｐ型
ＦＥＴ６．７が遮断して比較器２１の出力は下がってく
る。この結果、Ｐ型ＦＥ’ｌ’１６が導通して比較器２
２が動作を始める。端子２の電位が端子３のそれよシも
低いのだから、 Ｐ％ＦＥ’ｌ’１７は導通、Ｐ型ＦＥ
Ｔ１８は遮断となる。したがって、Ｎ型Ｆ’ＥＴ１９．
２０が導通して、出力５には電源端子４の電位が現れる
。この電位は同時にＮ型ＦＥＴ１４のゲートにも印加さ
れて、ＦＥＴｘ、ｉは遮断し、この結果、比較器２１は
動作を停止し、−ｔ′の出力を７０−ティングとする。Next, when the potential of the input terminal 2 becomes lower than the potential of the input terminal 3, the N-type FET 8 is cut off, the N-type FET 9 becomes conductive, the P-type FET 6.7 is cut off, and the output of the comparator 21 decreases. As a result, the P-type FE'l'16 becomes conductive and the comparator 2
2 starts working. Since the potential of terminal 2 is lower than that of terminal 3, P%FE'l'17 is conductive and P-type FE.
T18 is cut off. Therefore, N-type F'ET19.
20 becomes conductive, and the potential of the power supply terminal 4 appears at the output 5. This potential is simultaneously applied to the gate of the N-type FET 14, shutting off the FETs x and i, and as a result, the comparator 21 stops operating, and the output of -t' becomes 70-tings.
以上に述べたように、第２図の回路では、入力端子２と
入力端子３の電位の比較を行っているが、前述の説明か
ら、本回路において、出力Ｖ）整層時間を決定するもの
は、立上が多時にはＰ型ＦＪ！：Ｔ７の電流ドライブ能
力であシ、立下が多時にはＮ型ＦＥＴ２０の電流ドライ
ブ能力であることがわかる。As mentioned above, in the circuit shown in Fig. 2, the potentials of input terminal 2 and input terminal 3 are compared, but from the above explanation, in this circuit, the output (V) determines the layering time. When startup is frequent, P type FJ is used! : It can be seen that the current drive ability of T7 is the current drive ability, and when the fall occurs frequently, it is the current drive ability of the N-type FET 20.
本回路は前述のとおシ１足定常な状態では、一方のに″
Ｅ Ｔは遮断状態−に必るので１両Ｆ Ｅ ’ｒの電流
ドライブ能力を増大させても、定常時における消費電流
を増大させずにすむことがわかる。As mentioned above, this circuit operates in one foot in a steady state.
Since ET is required in the cut-off state, it can be seen that even if the current drive capability of one car FE'r is increased, the current consumption during steady state does not need to be increased.
以上のように、不発明によれは消費電流を増大させるこ
となく、出力の整定時間を短くすることの可能な比較回
路を提供できる。As described above, the present invention can provide a comparison circuit that can shorten the output settling time without increasing current consumption.
なお５本文眺明甲から明らかなように不発明は、ＣＭＵ
Ｓ （相補型式１０Ｓ）プロセス上でも実現が可能で６
！０ 、 Ａ／１）、 ｉ）／ｋ コンバータ等りア
ナログ／デジタル混在の集積回路においても、優れた比
較回路を提供するものであシ、その適用範囲は広く、こ
れによる実用上の利益は多大である。Furthermore, as is clear from the text view A of 5, the non-invention is CMU
S (complementary type 10S) can also be realized on the process6
! It provides an excellent comparison circuit even in analog/digital mixed integrated circuits such as 0, A/1), i)/k converters, etc., and its application range is wide, and the practical benefits from this are enormous. It is.
第１図は従来の比較回路の一例をかす回路図であシ、第
２図は本元明の一実施例＊ｙｒ、す回路図である。
１・・・・・・正電源端子％２・・・・・・入力端子、
３・・・・・・入力端子、４・・・・・負電源端子、５
・・・・・・出力端子、６・・・・・・Ｐ型ＰＥＴ、
７・・・・・・Ｐ型ＦＥＴ、８・・・・・・Ｎ型ＦＥＴ
、９・・・・・・Ｎ型ＦＥＴ、１０・・・・・・尾篭流
源、１１・・・・・・Ｐ型ＦＥＴ、１２・・・・・・尾
篭流源、１３・・・・・・寄生負荷容量、１４・・・・
・・Ｎ型ＦＥ’ｌ’、１５・・・・・・定電流源、１６
・・・・・・Ｐ型ＦＥＴ、１７・・・・・・Ｐ型ＦＥ’
ｌ’ 。
１８・・・・・・Ｐ型ＦＥＴ、１９・・・・・・Ｎ型Ｆ
ＥＴ、２０・・・・・・Ｎ型ＦＥＴ、２１・・・・・・
比較器、２２・・・・・・比較器。FIG. 1 is a circuit diagram of an example of a conventional comparison circuit, and FIG. 2 is a circuit diagram of an embodiment of Akira Honmoto. 1...Positive power supply terminal %2...Input terminal,
3...Input terminal, 4...Negative power supply terminal, 5
...Output terminal, 6...P type PET,
7...P-type FET, 8...N-type FET
, 9... N-type FET, 10... Ogo source, 11... P-type FET, 12... Ogo source, 13... ...parasitic load capacitance, 14...
...N-type FE'l', 15... Constant current source, 16
...P-type FET, 17...P-type FE'
l'. 18...P-type FET, 19...N-type FET
ET, 20...N-type FET, 21...
Comparator, 22... Comparator.
Claims (1)
二つの比較器を有し、出力信号が取シ得る第１の電位レ
ベルを一方の比較器が発生するようにし、前記出力情号
が取シ得る第２の電位レベルを他方の比較器が発生する
ようにし、さらに−万の比較器が動作状態にあるときは
他方の比較器は非動作状態にあるようにしたこと金特畝
とする比較回路。It has two comparators whose input ends and output ends are connected in common, one of the comparators generates a first potential level that the output signal can take, and the output information The other comparator generates a second potential level that can be obtained by the other comparator, and furthermore, when the second comparator is in the operating state, the other comparator is in the inactive state. Comparison circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58225819A JPS60117910A (en) | 1983-11-30 | 1983-11-30 | Comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58225819A JPS60117910A (en) | 1983-11-30 | 1983-11-30 | Comparator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60117910A true JPS60117910A (en) | 1985-06-25 |
Family
ID=16835292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58225819A Pending JPS60117910A (en) | 1983-11-30 | 1983-11-30 | Comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60117910A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5440253A (en) * | 1992-08-26 | 1995-08-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated comparator circuit |
| FR2805682A1 (en) * | 2000-02-28 | 2001-08-31 | St Microelectronics Sa | COMPARISON DEVICE WITH VERY BASIC CONSUMPTION |
| KR20190142227A (en) * | 2018-06-15 | 2019-12-26 | 에이블릭 가부시키가이샤 | Comparator and oscillation circuit |
-
1983
- 1983-11-30 JP JP58225819A patent/JPS60117910A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5440253A (en) * | 1992-08-26 | 1995-08-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated comparator circuit |
| FR2805682A1 (en) * | 2000-02-28 | 2001-08-31 | St Microelectronics Sa | COMPARISON DEVICE WITH VERY BASIC CONSUMPTION |
| US6366137B2 (en) | 2000-02-28 | 2002-04-02 | Stmicroelectrioncs S.A. | Very low-power comparison device |
| KR20190142227A (en) * | 2018-06-15 | 2019-12-26 | 에이블릭 가부시키가이샤 | Comparator and oscillation circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH057931B2 (en) | ||
| KR960011964B1 (en) | Output buffer device | |
| US5180965A (en) | Direct-current power source circuit with back gate control circuit for power MOS-FET | |
| US5929679A (en) | Voltage monitoring circuit capable of reducing power dissipation | |
| JPH10173511A (en) | Voltage level shifting circuit | |
| JPS5941609B2 (en) | Complementary MOS circuit device | |
| JPH07111448A (en) | Interface circuit and voltage virtical circuit therewith | |
| JPS60117910A (en) | Comparator | |
| JPS6070822A (en) | Semiconductor integrated circuit | |
| JP2769653B2 (en) | Inverting circuit | |
| JPS63314020A (en) | Integrated circuit for automobile | |
| JPH0677804A (en) | Output circuit | |
| JPH0935484A (en) | Voltage detection circuit of semiconductor memory device | |
| JPH04270513A (en) | Circuit used to drive floating circuit in response to digital signal | |
| JP3052433B2 (en) | Level shift circuit | |
| JPH01161913A (en) | Clock driver circuit | |
| JPH03175730A (en) | Output buffer | |
| JP2859898B2 (en) | Chopper type comparator | |
| JPH0430765B2 (en) | ||
| KR960015319B1 (en) | Semiconductor memory device of voltage conversion circuit | |
| JP2000055946A (en) | Voltage detector circuit | |
| JPH0225108A (en) | Semiconductor integrated circuit | |
| JPH0351780A (en) | Integrated circuit device | |
| JPH02145018A (en) | Level shift circuit | |
| JPS6022657Y2 (en) | Direct-coupled amplifier disturbance prevention circuit |