JPS6221324A - Logic integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a logic integrated circuit with high speed, low power consumption and high yield by constituting all gate circuits except a phase number converting circuit with gate circuits driving a couple of inverting/noninverting phases and outputting a couple of bipolar output signals. CONSTITUTION:In impressing signals with a phase difference of 180 deg. to input terminals I, the inverse of I respectively, the signals are amplified inversely by a differential circuit composing of field effect transistors (FETs) T1, T2 respectively. Then the signals are amplified by a level shift source follower circuit comprising FETs T3, T6 and another level shift source follower circuit composing of FETs T4, T7 and outputted from output terminals Q, -Q. In this case, the signals outputted from the output terminals Q, -Q have a phase difference of 180 deg.. Thus, high speed, low power consumption and high yield are attained.

Description

[Detailed description of the invention] "Industrial application field" This invention uses field-effect transistors to achieve high speed.

Related to logic integrated circuits with low power consumption and high manufacturing yield.

"Prior Art" Conventionally, basic gates (for example, inverter circuits) of logic integrated circuits that use current switching circuits composed of field effect transistors (FETs) and loads as internal gates are as shown in FIG. , has one input terminal I and one output terminal Q, and has a DC reference voltage V re
Those with f were commonly used.

[Problems to be Solved by the Invention] The purpose of the present invention is to provide a logic integrated circuit that is faster, consumes less power, and has a higher manufacturing yield than the logic integrated circuit using the conventional gate circuit described above. .

"Means for solving the problem" This invention solves all gate circuits except the phase number conversion circuit.
It is characterized by being configured with a gate circuit that is driven by a pair of input signals having a positive phase and a negative phase, and outputting a pair of output signals having a positive phase and a negative phase.

"Example" Hereinafter, an example of the present invention will be described with reference to the drawings. First, FIG. 1 shows the configuration of a basic gate circuit (inverter circuit) used in a logic integrated circuit according to the present invention. In this figure, t, T are input terminals, Q,
Q is each output terminal, 1st to 7th are FET, R7, )"(
2 is the load resistance, mata, Vcs is PET-5th to T
7, the gate voltage Vss is the power supply voltage. In such a configuration, when signals having phases different by 180° are applied to the input terminals I and T, these signals are applied to the input terminals I and T respectively.
1, the second differential circuit is inverted and amplified, and then the FET-third . Source follower circuit and FET for level soft consisting of 6th - 4th. The signal is amplified by the seventh source follower circuit and output from output terminals Q and Q. In this case, the signals output from output terminals Q and Q each have a phase of 180 degrees. Furthermore, 1? ET-Is the fifth fixed? This is a FET that constitutes the lit & circuit.

Next, the first embodiment of the present invention will be explained. Fig. 2 is a block diagram showing the configuration of the first embodiment of the present invention. For,
This is a circuit that obtains the following logic operation output.

(A+ii→-C)・(D1E+F)・・・・(1)
In Fig. 2, 1 to 6 are 411/double-phase conversion circuits that each convert a signal of the school into a signal of both phases, 7.8 is a j3-man power circuit with two-phase output, 9 10 is a double-phase/single-phase conversion circuit that converts double-phase input to single-phase output. 10 is a double-phase/single-phase conversion circuit that converts double-phase input to single-phase output. In the figure, the solid line is the positive phase, and the broken line is the Indicates a signal line with opposite phase.

As shown in this figure, in the logic integrated circuit of the present invention, all the gate circuits inside the one-dot-dashed line are constituted by two-phase input and one-two-phase output gate circuits. In the embodiment shown in Fig. 2, single-phase/double-phase conversion circuits 1 to 6 and dual-phase/single-phase conversion circuits 10 are provided, or the entire integrated circuit including the input/output circuit is operated for dual use. Of course, this is also possible.

Figures 3 to 6 respectively show the above-mentioned injection/double III conversion circuits 1 to 6.3 human power OR circuit 7, 8.2 human power AND circuit 9.
, is a circuit diagram showing a specific configuration example of a dual-phase/single-phase conversion circuit 10. FIG. In this case, the symbol L in Fig. 1, Fig. 5
S is a diode or a resistor (,.

Therefore, it is a level soft path composed of
In the figure, 13 is a connection line such as a coaxial cable that connects to an external circuit, and resistors 14 and 15 are input resistors (in the case of level EC1) connected to the input end of the external circuit.

7 to 9 are circuit diagrams showing +14 configurations of the second to fourth embodiments of the present invention, respectively, in which FIG. 7 is an exclusive OR circuit, and FIG. 8 is a D-type flip-flop circuit. , Figure 9 is 4
-1 selector circuit. Note that these circuits are only examples, and the present invention can of course be applied to various other logic circuits.

“Effects of invention-1 According to this invention, it is faster than the conventional one.

The effects of low power consumption and high manufacturing yield can be obtained. The reason for this will be explained below in a comparison with the conventional circuit shown in FIG. 10 using the basic gate circuit shown in FIG. 1 as an example.

■High speed FIG. 11 shows the input/output transfer characteristics of the conventional circuit.

In this figure, the change in the potential at point A and the change in the potential at the output terminal Q in FIG. 10 are shown by a solid line LI and a broken line L2, respectively. The logic amplitude and input uncertainty voltage width, which characterize this transfer characteristic τ, are IV (281, △Vi
When n, IV(!sl is determined by the following formula.

l VQsl −l R+x I, l=R,・I,
(2) Here, R is the value of the load resistance, and 1° is the T current of the FET 4'r,1 that constitutes the constant current circuit. On the other hand, ΔVin is determined by the following formula A1.

△V in= 2 (V qson-V th) □・-
(3) Here, V9son is PET-T in FIG.
I.

The second is the gate-source voltage required for the current ()1 to flow. Figure 12 shows iA11 and V@son.
Indicates the relationship between Further, vth is a threshold voltage.

For simplicity, I”　E　i”・1゛l.

Second. It is assumed that the fourth gate width is the same and is W9.

By the way, in the logic circuit, the gain G defined by the following equation (4) must be equal to the equation (5) equal to 11.

G=lV+2sl/△V in--(4) G≧1...
(5) Therefore, in the conventional circuit shown in FIG. 1O, the load resistance R+ must satisfy the following equation.

R5≧2(V9son-Vth)/I +・−・・(
6) On the other hand, in the case of the circuit shown in FIG. 1, 1VQs1. △Vi
Each n is expressed by the following formula.

l V12Sl = Rzl ,...(7)△V
in=V9son-VLh...-(8) Substituting these equations (7) and (8) into equation (4) above, and then into equation (5), R7≧(V gson -V th)/I +--(
9) is obtained.

As is clear from comparing this equation (9) and the above equation (6), the conventional circuit shown in Fig. 1O has twice the value of the load resistance compared to the circuit shown in Fig. 1. As a result,
The capacitance connected to the load resistance (I?' in the case of Figure 1θ)
Input capacitance of ET-T 3, FET-T in the case of Figure 1
3. The time constant for driving the input capacitance of T4 is doubled.

That is, the circuit of FIG. 1 has a faster response speed than the conventional circuit of FIG. 1O.

Incidentally, FIG. 13 shows the input/output transfer characteristics of the circuit of FIG. 1. In this figure, a solid line L3 indicates the potential at point A in FIG. 1, and a dashed line L4 indicates the potential at the output terminal Q.

■Low power consumption Conditions for the high-speed operation of the current switching circuit in Figure 1O or Figure 1 (region where the gate-drain capacitance C9d is small)
It is necessary that the drain-source voltage V ds, gate-source voltage V9s, and threshold voltage vth of FET-Tl and T2 have the following relationship.

V ds> V gs −V th−・= (10) Therefore, in order for the conventional circuit shown in FIG. 1O to satisfy equation (lO) in all operating states, the reference voltage V
ref needs to satisfy the following equation.

V ref≦−(1,51VCsl−Vth)−−(
11) Now, FET-T1. T2. Assuming that T4 has the same characteristics (same gate width, V th, and 19son) and that G=1, (2), (3), (4), (
From formula 11), V ref≦-(1,5・2(Vcs-Vth)-Vt
h)=(3Vcs-4Vth)·-(12) is obtained. Now, considering the case where this equation (12) has an equal sign, when FET -T 2 is in the on state, the potential Vc at the 0 point in FIG. 1O becomes the following equation.

V c= V ref −V cs −−4(Vcs−Vth)・=・(l 3)PET-T
When formula (lO) is applied to 4, the power supply voltage Vss needs to be as follows.

Vss≦V c −(V cs −V Lh)−15(
Vcs-Vth)...=...(14) On the other hand, in the circuit of FIG. 1, the condition for Vss that satisfies equation (10) in all operating states is Vss<-l V(2sl-2 (Vcs-Vth)
-(15) is obtained. Also, the above equation (8) and G
From the condition of =1, l V12sl ==Vcs-vth-...(1
6) is obtained, and therefore, Vss≦-3(V as -V th)...-(17)
The following formula is obtained.

However, as is clear from comparing equation (17) and equation (14) above, the circuit of FIG.
The conventional circuit 315 shown in FIG. That is,
According to the present invention, when designed to flow the same current,
The power consumption is 315 times lower than that of the conventional circuit, making it possible to reduce power consumption.

■High manufacturing yield When integrating FETs, the vth of the FETs fluctuates within the chip. Accordingly, the output level of each internal gate fluctuates. This output level is also the input level of other internal gates. Here, Fig. 1θ.

In FIG. 11, for example, when the human-powered high level Vinh changes due to the fluctuation of vth, Vrer, which is a logical threshold value,
If the potential becomes lower, what should be a high level will be identified as a low level, causing malfunction. In this way, in the conventional circuit, the voltage V ref becomes a logical threshold, and if the fluctuation of vth increases beyond a certain range, malfunctions will inevitably occur.

On the other hand, in the present invention, FET-T1, T
If the two thresholds are the same, there is basically no absolute logical threshold. Therefore, since there is a wide tolerance range for variations in Vth, deterioration in yield due to variations in Vth is extremely small. Note that since FETs in the same gate are usually located very close to each other in the chip, they have almost the same threshold value.

Note that if even one single-phase current switching circuit is included as an internal logic gate in an integrated circuit, the following drawbacks occur.

(A) A single current switching circuit has V12s as described above.
Since the voltage is large, the power supply voltage Vss for normal operation is
is large. Therefore, if the internal gates of both phases and Vss are made common, the low power consumption of the two-phase circuit will be impaired. In order to avoid this, it may be possible to use different power supplies for the dual-phase internal gate and the single-phase internal gate, but in this case, the number of power supplies increases, which is not practical.

<B), internal logic gates operating in the rlx phase operate slower than in both phases. Here, in a sequential logic circuit using a clock, the operating speed of the entire integrated circuit is
Since it is determined by the operating speed of the slowest internal logic gate,
If there is even one single-phase internal gate, the speed of the entire integrated circuit will be the operating speed of the single-phase internal S logic gate, and the high speed of the dual-phase internal gates will not be utilized.

On the other hand, in the present invention, since all dual-phase current switching circuits are used as internal logic gates, the above-mentioned drawback does not occur.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the deadwood circuit of the internal logic gate used in the embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the first embodiment of the invention, and FIGS. 3 to 6 are circuit diagrams showing the configurations of single-phase to double-phase conversion circuits 1 to 6, OR circuits 7 and 8, AND circuit 9, and double-phase to single-phase conversion circuit 10 in FIG. 2, respectively, and FIGS. Figure 9 shows the second to third figures of this invention.
A circuit diagram showing the configuration of the fourth embodiment, FIG. 10 is a circuit diagram showing the configuration of an internal gate circuit used in a conventional logic integrated circuit, and FIG. 11 is an input/output transfer characteristic of the circuit in FIG. 10. 12 is a diagram showing the drain voltage-drain current characteristics of the FET, and FIG. 13 is a diagram showing the input/output transfer characteristics of the circuit of FIG. 1. Tl-T7...FET, R2...Load resistance, 1-6...Single-phase/double-phase conversion circuit, 7, 8
...OR circuit, 9...AND circuit, I
O...Double-phase/single-phase conversion circuit. Figure 1 Figure 2 Figure 3 Figure 5 Figure 6 Figure 7 @ Figure 8 Figure 1θ Figure

Claims (1)

[Claims] In a logic integrated circuit that uses a current switching circuit consisting of a field effect transistor and a load as a unit gate circuit, all gate circuits except the phase conversion circuit are connected to a pair of inputs consisting of a positive phase and a negative phase. A logic integrated circuit consisting of a gate circuit that is driven by a signal and outputs a pair of output signals of positive phase and negative phase.