JPS6051322A - Cmos voltage converting circuit - Google Patents

Abstract

PURPOSE:To convert an input signal from a low-voltage power supply system to a signal of a high-voltage power supply system by charging a capacitor beforehand and superposing a voltage between both ends of the capacitor onto an input voltage to drive a CMOS inverter of the high-voltage power supply system. CONSTITUTION:An input signal Vi is the signal of the low-voltage power supply system, and a transistor TRT1 is turned off when the input signal Vi is 0V. A voltage obtained by subtracting a voltage drop VF due to a diode from a power source voltage VP is applied to a capacitor C; and since this voltage is set to a value smaller than the value obtained by subtracting a threshold VTP (absolute value) of a TRT2 from a high voltage VPP, the TRT2 is turned on, and a high voltage is outputted to an output VO. When the input signal Vi starts rising to VCC, TRs T1 and T2 are turned on together; and when the input signal Vi rises furthermore, the TRT2 is turned off, and the output VO is 0V.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a CMOS (complementary insulated gate semiconductor device)
The present invention relates to circuits, and particularly to a CMOS voltage conversion circuit for converting signal voltages between low voltage power supply circuits and high voltage power supply circuits.

[Technical background of the invention]

This type of conventional CMOS voltage conversion circuit was constructed as shown in FIG. That is, the amount of v is the low voltage power supply vcc
(For example, +5V) input voltage from a system circuit,
Its variation range is Ov to +5v. T1 is an N-channel MOS-FET (field effect transistor, hereinafter simply referred to as a transistor), the input voltage vi is input to its gate, its source is grounded, and its drain is connected to the drain of a P-channel MO8 transistor T. be done.

The gate of this P-channel transistor T is grounded, and the source is a high voltage power supply Vpp (for example, +-20V
)It is connected to the.

Thus, when the input voltage Vt is Ov, the driving transistor TI is turned off, and the pp power supply voltage appears at its drain through the load transistor T.

On the other hand, when the input voltage Vt is +5■, the driving transistor T1 is turned on and the voltage at its drain becomes OV.

[Problems with background technology]

In the above voltage conversion circuit, a load element (transistor T, ) is required, and if the load of the driving transistor T is large, a large driving force is required to set the drain voltage (output voltage) to Ov. At the same time, a large current flows, and if the load is reduced, there is a problem that it takes time to completely bring the drain voltage to Ov when the driving transistor T is turned on. Further, while the input voltage Vt is +5V, the driving transistor Ti is turned on, and Vpp power supply → load transistor T, → driving transistor T, →
Since direct current flows through the grounding path, there is a drawback that current consumption increases.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is capable of converting input signals from a low-voltage power supply system into signals from a high-voltage power supply system, consumes little current, and provides a sufficiently large voltage range of the converted output signal. The present invention provides a CMOS voltage conversion circuit that can perform the following steps.

C. Summary of the Invention] That is, the CMOS electrician conversion circuit of the present invention includes a first MOS transistor T1 of the first conductivity type and a second conductivity type transistor T1 between the first reference power source V s 8 and the second reference power source Vpp. the second M of
OS) A transistor Tt is connected in series, a capacitor ct- having a capacitance larger than the gate capacitance of the second transistor T is connected between the gates of both transistors, and a third reference power supply Vp and a second transistor T2 are connected in series. 1st between
A second diode D2 is connected between the gate of the second transistor T2 and the M2 reference power supply vpp, and an input signal from the low voltage power supply system is connected to the gate of the first transistor TI. Guiding,transistor T,,
This is characterized in that a converted signal of the voltage power supply system is derived from the connection point of Tt.

(Embodiment of the Invention) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a CMOS voltage conversion circuit formed in a MOS integrated circuit, where A is an input node and an input voltage V1 is derived from a V a e power supply system circuit, which is a low voltage system. TI is an N-channel enhancement type MOS transistor whose gate is connected to the input node A and whose source is connected to the first reference power supply vBs.

T! It is an idP channel encoder type MOS transistor, and its source is connected to the high voltage VPp power supply which is the second reference power supply, and the input is the MO8).
It is commonly connected to the drain of the transistor T1 and is also connected to the output node E, and its gate is connected to the input node A via the capacitor C. On the other hand, the third reference power supply Vp is connected to the capacitor fC and the MOS transistor T! through the first diode D1 in the forward direction. The node B is connected to the node B), which is connected to the Vpp power supply via the second diode D in the forward direction.

Note that the capacitor fC has a capacitance of P channel M
O8) It is formed to be sufficiently larger than the gate capacitance of transistor Tt.

Next, the operation of the CMO8 voltage conversion circuit will be explained with reference to FIG. Here, N-channel transistor T,
Let VTy be the threshold voltage of P-channel transistor T, vTP be the threshold voltage of P-channel transistor T, and V be the forward voltage of first diode D.

First, when the input voltage V1 is Ov, the N-channel transistor T is off, and the voltage V)3 at node B is VB
−=IVP−VF, and Vp−vF〈Vpp IVT
If it is designed to be PI, the P channel transistor T2 will be on, and the output voltage of the output node E will be vF,
is VB-vpp.

Next, when the input voltage vi rises from 0■→Vcc, V
As l increases, vB also increases, and since the capacitance of capacitor C is sufficiently larger than the gate capacitance of P-channel transistor T, the voltage across capacitor yfc (VB-Vi)
When Vl-OVO (D VB (-V p V y
) is maintained. When the input voltage Vt reaches VTH, the N-channel transistor T turns on. At this time, V
B-VTN+Vp-vP, if vTN+Vp-v
.

If <Vpp IVTPI, the P-channel transistor T also remains on at this point.

Vl further increases to vTN+vp VF-Vpp-IV
When Tpl is reached, the P-channel transistor T is turned off and the output voltage Vδ becomes OV.

Note that the maximum value of the voltage at node B is the voltage of the second diode D,
can be suppressed to VPP by If this diode D is not present, the voltage VB at the node B becomes too high, which adversely affects the circuit operation.

According to the CMO8 voltage conversion circuit as described above, signal voltage conversion from the low voltage system Vcc to the high voltage system Vl)p is possible. Then, when the input voltage Vt reaches a predetermined value, P
The gate potential of the channel transistor T (voltage VB at node B) completely turns off the transistor T by the boosting action of the capacitor C, so the output voltage vr at this time becomes completely Ov, and the converted output signal The voltage range is large. Also, in a stable state, the vpp power supply and V
No direct current flows between it and the sg power supply, so current consumption is low.

Note that as the first diode D1, one or more N-channel enhancement type transistors whose drains and gates are connected to each other may be connected in series, or N-channel enhancement transistors whose drains and gates are connected to each other may be used. P
One or more channel enhancement type transistors connected in series may be used. That is, in the circuit of FIG. 4, two N-channel transistors TjsT4 are used for the first diode, and the transistor TjsT4 is used for the first diode.
The drain and get of transistor T4 are connected to the Vp power supply, the source is connected to the drain and gate of transistor T3, and the source of transistor T8 is connected to node B. Further, in the circuit of FIG. 5, two P-channel transistors TM are used for the first diode.

Using T6, the source of the transistor T6 is connected to the Vp power supply, the drain and gate are connected to the source of the transistor TI(7), and the drain and gate of this transistor T are connected to the node BK.

In the circuits shown in FIGS. 4 and 5, the above-mentioned second
The same parts as those in the figure are given the same reference numerals. In addition, in the circuit of FIG. 5, P-channel transistors T, , T,
By connecting the substrate region (N type) of transistor T to the highest potential end (vpp power supply), the PN junction existing between the source and substrate regions of transistor T is connected to the second diode (second
Available as Figure nt).

In the above embodiment, positive voltages were used as the Vee, Vpp, and Vp power supplies, but when negative voltages are used, the P channel and N channel of the transistors used may be reversed.

〔Effect of the invention〕

As described above, according to the CMO8 voltage conversion circuit of the present invention, it is possible to convert an input signal from a low voltage power supply system to a signal from a high voltage power supply system, the current consumption is small, and the voltage range of the conversion output signal is sufficiently wide. It is possible to take

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional CMO8 voltage conversion circuit, Fig. 2 is a circuit diagram showing an embodiment of the CMO8 voltage conversion circuit according to the present invention, and Fig. 3 is shown to explain the operation of Fig. 2. The characteristic diagrams, FIGS. 4 and 5 are circuit diagrams showing other embodiments, respectively. T, ~T4...MOS) transistor, C...capacitor, DllD! ...Diode, A...Input node, E...Output node, Vss, Vpp + v
p...Power supply. Applicant's agent: Patent attorney Hiko Etake Figure 1 Figure 2

Claims (1)

[Claims] (1) MO8)7 transistor T of the first conductivity type whose gate is connected to the input node A, whose source is connected to the first reference power supply, and whose drain is connected to the output node;
8) A drain is connected to the drain of transistor T1,
MOS of the second conductivity type whose source is connected to the second reference power supply
Transistor T! and these MO8) transistors TI
eT! A capacitor C is connected between the gates of the MO8) transistor T and has a capacitance larger than the gate capacitance of the MO8) transistor T;
a first diode D connected between the reference power source; and
Similarly, MO8) transistor T. a second diode D connected between the gate of the CMO and the second reference power source.
Swt pressure conversion circuit. Q) As the first diode, one MOS transistor of the first conductivity type whose drain and gate are connected to each other is used as the first diode.
Use one or more connected in series, and the drain
The CMOS voltage conversion circuit according to Patent 1, wherein the gate interconnection side is connected to the third reference power supply, and the source side is connected to the gate of the MO8 transistor T. {3} As the first diode, one or more MOS transistors of the second conductivity type whose drains and gates are connected to each other are connected in series, and the source side thereof is connected to the third reference power source. , the drain-gate interconnection side of the cyxos'#! according to claim 1 is connected to the gate of the MOS}transistor T. i-pressure conversion circuit.