JP2000132989A - Track hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high speed and a high accuracy by providing a first switch connected to a first buffer circuit, a second switch connected to a second buffer circuit, a third and a fourth buffer circuits having respective inputs connected to the first and second switches, and a first and a second capacitors connected respectively to the third and fourth buffer circuits. SOLUTION: At a track mode, sampling switches SW1 and SW2 are closed and output signals of first and second buffer circuits 9 and 12 become voltages following in accordance with input signal voltages Vin and *Vin. At a hold mode, the sampling switches SW1 and SW2 are opened, a voltage charged in capacitors 11 and 14 immediately before the opening is held, and output voltages of buffer circuits 10 and 13 are held to conform to the voltage held in the capacitors 11 and 14. Output signals of buffer circuits 9 and 12 are leaked to buffer circuits 10 and 13 via parasitic capacities of switches SW1 and W2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a track-and-hold circuit for capturing a high-frequency signal, and more particularly to a track-and-hold circuit suitable for use in a stage preceding an AD converter.

[0002]

2. Description of the Related Art In general, it is difficult to convert an analog signal that changes very quickly to digital with an AD converter with high accuracy. However, by providing a track-and-hold circuit that follows a signal and holds the voltage value of the signal at a certain timing before the AD converter, a high-frequency signal can be converted to digital with high accuracy.

In general, there are two types of track-hold circuits: an open-loop configuration shown in FIG. 3 and a closed-loop configuration shown in FIG. In the track and hold circuit of FIG. 3, an input signal Vin is applied to an input buffer circuit 1, a capacitor 3 for holding a voltage is connected to an input of an output buffer 2, and an output of the input buffer 1 A sampling switch 4 controlled by a timing signal is provided between the output buffer 2 and the input of the output buffer 2. On the other hand, in the track and hold circuit of FIG. 4, an operational amplifier is used for the input buffer circuit 5 and the output buffer circuit 6, and the input signal Vin is input to one input of the input buffer circuit 5.
Is applied, and the output of the output buffer circuit 6 is fed back to the other input. A capacitor 7 for holding a voltage is connected to the output of the output buffer circuit 6 and one input thereof, and the other input is connected to a predetermined potential, for example, a ground potential. A sampling switch 8 is provided between the output of the input buffer circuit 5 and one input of the output buffer circuit 6.

In the track and hold circuits of FIGS. 3 and 4, when the sampling switches 4 and 8 are off, the input buffer circuits 1 and 5 can obtain output signals that follow the voltage of the input signal Vin. When the sampling switches 4 and 8 are turned on, the output voltages of the input buffer circuits 1 and 5 are held in the capacitors 3 and 7. When the sampling switches 4 and 8 are turned off, the voltages held in the capacitors 3 and 7 are output from the output buffer circuits 4 and 6, and the voltages are kept held.

The features of the open-loop track-and-hold circuit shown in FIG. 3 have a simple structure and a high speed, but have the disadvantage that accuracy is poor because there is no feedback loop. A feature of the track-hold circuit having the closed loop configuration shown in FIG. 4 is that high accuracy can be obtained because of including the feedback path, but there is a disadvantage that the operation speed is reduced due to the influence of the feedback path. .

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a track-and-hold circuit having both high speed and high accuracy, and an object of the present invention is to improve the accuracy of an open-loop track-and-hold circuit. Then, as a result of examining the cause of the deterioration of the accuracy of the track-hold circuit having the open loop configuration, one of the factors was found.

The sampling switch 4 shown in FIG.
Although it is composed of an OS transistor, a parasitic capacitance exists between its source and drain. When the input signal is a high-frequency signal, the impedance of the parasitic capacitance decreases. Therefore, even when the sampling switch 4 is in the off state during the hold, the buffer circuit 1
Is transmitted to the buffer circuit 2, and the held voltage changes. As a result, the accuracy of the track hold circuit has deteriorated.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and is provided with first and second buffer circuits to which input signals complementary to each other are applied, respectively, A first switch connected to the output of the first buffer circuit, a second switch connected to the output of the second buffer circuit, and a third buffer having an input connected to the first switch A circuit, a fourth buffer circuit having an input connected to the second switch, a first capacitor connected to an input of the third buffer circuit, and a circuit connected to an input of the fourth buffer circuit. A second capacitor, a first dummy switch provided between an output of the first buffer circuit and an input of the fourth buffer circuit, and a second dummy switch provided between the second buffer circuit and the fourth buffer circuit. Provided between inputs In which track and hold circuit with high accuracy can be realized by providing the second dummy switch.

Further, the first and second switches are M
The first and second dummy switches are constituted by OS transistors, and the first and second dummy switches are constituted by MOS transistors of the same size as the MOS transistors of the first and second switches, so that a highly accurate track and hold circuit can be realized. Things.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, in which two systems of open-loop type track-and-hold circuits are used, and each input signal has a complementary relationship, that is, Vin. And a track hold circuit to which the inverted signal * Vin is applied.

A sampling switch SW1 is provided between the first buffer circuit 9 and the third buffer circuit 10 to which the input signal Vin is applied.
Is connected to the ground potential GND. On the other hand, the second buffer circuit 12 and the fourth buffer circuit 1 to which the inverted input signal * Vin is applied
3, a sampling switch SW2 is provided, and a voltage holding capacitor 14 is provided between the input of the fourth buffer circuit 13 and the ground potential GND. Furthermore,
The output of the first buffer circuit 9 and the fourth buffer circuit 13
, A dummy switch SW4 is provided, and between the output of the second buffer circuit 12 and the input of the third buffer circuit 10, a dummy switch SW3 is provided. The dummy switches SW3 and SW4 are formed in exactly the same size as the sampling switches SW1 and SW2. However, the dummy switches SW3 and SW4 are always open and are not closed in the track mode and the hold mode.

In the track hold circuit shown in FIG. 1, in the track mode, the sampling switch S
W1 and SW2 are in a closed state. Therefore, the first
The output signal voltage of the buffer circuit 9 and the second buffer circuit 12 becomes a voltage that follows the input signal voltages Vin and * Vin, and this voltage is applied to the capacitors 11 and 14 via the sampling switches SW1 and SW2, respectively. Charged. Also, the output voltages Vout and * Vou of the third buffer circuit 10 and the fourth buffer circuit 13
t is also a voltage that follows according to this voltage.

In the hold mode, the sampling switches SW1 and SW2 open. Immediately before the switches SW1 and SW2 are opened, the voltages charged in the capacitors 11 and 13 are held, and the output voltages of the buffer circuits 10 and 13 are held at voltages corresponding to the voltages held in the capacitors 11 and 13. At this time, the buffer circuits 9 and 1
2 is leaked to the buffer circuits 10 and 13 via the parasitic capacitances of the switches SW1 and SW2, respectively, but the output signal of the buffer circuit 9 is output to the dummy switch SW3.
, And the output signal of the buffer circuit 12 leaks to the input of the buffer circuit 10 via the parasitic capacitance of the dummy switch SW4. Here, the dummy switches SW3 and SW
Since 4 is formed in the same size as the sampling switches SW1 and SW2, the signals leaked to the input of the buffer circuit 10 via the switch SW1 and the dummy switch SW3 have opposite phases and the same level. Therefore, these leaked signals cancel each other out, and consequently, the voltage change of the input signal of the buffer circuit 10 does not occur. The same applies to the input of the buffer circuit 13. FIG. 2 is a specific circuit diagram of the track and hold circuit shown in FIG. First buffer circuit 9
The second buffer circuit 12 includes low-current sources 15 and 16 and P-channel MOS transistors 17 and 18 connected in series between the power supply Vdd and the ground GND. Is taken as output. That is, a source follower is configured. Also, the sampling switches SW1 and SW2
Are composed of N-channel MOS transistors 19 and 20, respectively, and a control signal CLK for controlling the track mode and the hold mode is applied to the gates thereof.
Each of the dummy switches SW3 and SW4 has an N-channel M
Although constituted by OS transistors 21 and 22, the gate is connected to the ground GND. Therefore, the MOS transistors 21 and 22 are always off. Furthermore, MOS
The transistor size of the transistors 21 and 22 is MO
It is formed in the same manner as the S transistors 19 and 20. Therefore, the parasitic capacitance between the source and the drain of the MOS transistors 19 and 20 and the parasitic capacitance between the source and the drain of the MOS transistors 21 and 22 are the same, and the leaked voltage level is also the same. Therefore, the leak voltage transmitted to the inputs of the buffer circuits 10 and 13 is canceled.

[0014]

As described above, according to the present invention, a phenomenon in which a high-frequency signal leaks through a sampling switch, that is, feedthrough is prevented in the hold mode of a track and hold circuit, and the influence on an output signal is reduced. It can be eliminated. As a result, a high-speed and high-accuracy track hold circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a specific circuit diagram of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a conventional open loop type track and hold circuit.

FIG. 4 is a block diagram showing a conventional closed loop type track and hold circuit.

[Explanation of symbols]

 9 First buffer circuit 10 Third buffer circuit 11 Capacitor 12 Second buffer circuit 13 Fourth buffer circuit 14 Capacitor 15, 16 Constant current source 17, 18 P-channel MOS transistor 19, 20 N-channel MOS transistor 21, 22 N-channel MOS transistor

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yasuyuki Kimura 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (2)

[Claims] 1. A first and a second buffer circuit to which input signals complementary to each other are respectively applied, a first switch connected to an output of the first buffer circuit, and the second buffer A second switch connected to an output of the circuit, a third buffer circuit having an input connected to the first switch, a fourth buffer circuit having an input connected to the second switch, A first capacitor connected to an input of a third buffer circuit, a second capacitor connected to an input of the fourth buffer circuit, an output of the first buffer circuit, and the fourth buffer circuit And a second dummy switch provided between the inputs of the second buffer circuit and the fourth buffer circuit. 2. The method according to claim 1, wherein the first and second switches are MOS.
A track and hold circuit comprising transistors, wherein the first and second dummy switches are composed of MOS transistors of the same size as the MOS transistors of the first and second switches.