JPH0354903B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS transistor circuit suitable for integration into an integrated circuit.

In general, the number of external lead-out pins (terminals) led out from a package of a MOS integrated circuit is preferably as small as possible from the viewpoint of downsizing the package. One solution to this problem is to share the external pins of the integrated circuit, but when considering sharing the signal line and power supply line, the input signal capability is added to the common node of these lines. (+10μA~-
Since it is a problem to flow a current of more than 10 μA), it is necessary to suppress the current value within the capability range.

The present invention has been made in view of the above points, and has a structure in which a current exceeding the capacity range does not flow between a power line to which a high potential is selectively supplied and a normally used power supply or ground, and the pin The present invention aims to provide a MOS transistor circuit that can solve problems in reducing the number of transistors.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram before the improvement leading to the present invention. Note that the channel types of the MOS transistors used here are all the same, for example, N-channel type. In Figure 1, 1 is an enhancement type for driving in which control signal A is input to the gate.
This transistor 1 is a MOS transistor, and its source is connected to a voltage Vs (ground potential) supply terminal, and its drain is connected to an output terminal O. Depletion type MOS transistor 2 as a load element
has its source and gate connected to the output terminal O,
A drain is connected to node a. This node a
is connected to the source of an enhancement type MOS transistor 3, and the drain and gate of the transistor 3 are connected to the supply end of the voltage Vp. The supply end of this voltage Vp serves as a signal line and a power supply line. Further, the source of a depletion type MOS transistor 4 is connected to the node a,
The drain of the transistor 4 is connected to the supply end of the voltage Vc as a normal power supply, and the gate is connected to the supply end of the control signal B.

Next, the operation of the circuit shown in FIG. 1 will be explained. First the voltage
When using the Vp supply line, that is, node b, as a signal line, signal B is set to "1". At this time, even if signal A is "1" and transistor 1 is turned on (conducting) and node o becomes "0", node a
The sizes of transistors 4, 2, and 1 and the threshold voltage Vth are set so that a potential near Vc (for example, +5 V) is output. Then, since the potential of node a is near Vc, the voltage Vp becomes
potential and the threshold voltage of transistor 3
No current flows through the transistor 3 below the sum of V _th3 and V th3. In other words, transistor 3 is in an off (non-conducting) state. By the way, the above signal Vp is
When using this as an input signal for other circuits, the maximum voltage is usually "Vc + 1" volts, and the potential of node a is around Vc, so if V _th3 is set around 1V, when Vp is the input signal, it will be the same. Almost no input current flows, and it can be used as an input signal for other MOS transistor circuits.

Next, when using Vp as a power source (for example, 25V), set signal B to "0". At this time, the circuit of FIG. 1 can determine the output 0 mainly by transistors 3, 2, and 1, and if the potential of node a is set to such an extent that transistor 4 is turned off,
No current flows from the Vp supply end to the Vc supply end. That is, Vp as a power source can be used in a state where Vc≦Vp, and a potential of “Vp−V _th3 ” volts can be output to node o.

In the circuit shown in FIG. 1 that operates as described above, it is not necessary to flow a current exceeding the capacity of the input signal to the node b, so that it is possible to reduce the number of pins when integrated into an integrated circuit.

Figures 2 and 3 are modifications of Figure 1, and in Figure 2, an enhancement type transistor 4' is used in place of the depletion type transistor 4 in Figure 1, and its gate is connected to the drain side. In FIG. 3, an enhancement type transistor 4'' is used in place of the depletion type transistor 4.

In Figure 4, the source of transistor 3' is connected instead to the drain side of transistor 3, which was connected to Vp, and connected to the drain circle Vp (node b) of transistor 3', and the control signal C is connected to the gate.
This is what you entered. In the example of FIG. 2, the threshold voltage V _th3 of transistor 3 is set higher than the threshold voltage _th4 ' of transistor 4', and
In the example shown in the figure, if V _th3 of transistor 3 is made higher than the threshold V _th4 of transistor 4, the "1" level of the input signal when Vp is used as a signal line can reach a potential higher than Vc without leakage current. Can be used. The above V _th3 is V _th4 ′,
To make V _th4 higher than ``V th4'', use the short channel effect, and in Figure 2, transistor 3
This can be easily achieved by making the channel length of transistor 4' shorter than that of transistor 4'' in Figure 3, or by making the channel length of transistor 4'' shorter than that of transistor 3 in Figure 3.In addition, in Figures 2 and 3, Vc is also used for signal and power supply as well as Vp. Can be used for both.

The example shown in FIG. 4 is designed so that when node b is used as a power source, a higher voltage is output at the output o than in FIG. 1. Signal C is a signal with the opposite phase to signal B. For example, if C is created using the circuit shown in Figure 1, the "1" level of C will be Vp (for example,
25V) becomes negative V _th3 . When b is used as a signal line, C is at "0" level and B is at "1" level. If the “0” level of C is set to 0V,
The potential of b' is only equal to or less than the absolute value of V _th3 ' of transistor 3'. Because (potential of b') = (potential of C - V _th3 '). To cut off transistor 3, |V _th3 ′|+V _th3 <(a
V _th3 (positive value) and V _th3 ′ should be selected so that the equation (potential) holds true. When b is used as a power source, a voltage of Vp-V _th3 (when made using the circuit shown in FIG. 1) is applied to C. When the potential of a is set near Vc, from the relationship of the formula, V _th3
If you set it to a value slightly above 0V, the first
It can be made to a much lower value than V _th3 used in the figure. At this time, it is easy to determine V _th3 ' within the range of the formula so that the level of b' reaches Vp, and the value of the output O can be determined only by the relationship of Vp - V _th3 , as shown in Figure 1. As much as the value of V _th3 in FIG. 4 can be made smaller than V _th3 in FIG. 4, a higher voltage can be outputted to the output O.

Note that the present invention is not limited to the above-mentioned embodiments; for example, an enhancement type transistor may be used as the depletion type transistor 2 as the load MOS, and its gate may be connected to the node a side, or a voltage Vc may be applied to the gate. You can also supply it.
Furthermore, although N-channel type transistors were used as the transistors in the embodiments, various applications are possible without departing from the gist of the present invention, such as a structure using P-channel type transistors.

As explained above, according to the present invention, it is not necessary to flow a current exceeding the capacity in the power supply line to which a high potential is selectively supplied, and the number of pins can be reduced, making it possible to miniaturize the integrated circuit, etc. had the advantage of
This is what a MOS transistor circuit can provide.

[Brief explanation of drawings]

1 to 3 are circuit diagrams before the present invention, and FIG. 4 is a circuit diagram of one embodiment of the present invention. 1, 3...Enhancement type MOS transistor, 2,4,3'...Depression type MOS transistor, a, b, o, b'...Node, Vp...
...Power supply voltage that selectively becomes high potential, Vc...Normal power supply voltage, Vs...Earth voltage, A, B, C...
Control signal.

Claims (1)

[Claims] 1 a first MOS transistor for driving whose one end is connected to a first potential supply end;
a second MOS transistor for a load, one end of which is connected to the other end of the transistor; and at least one depletion transistor, one end of which is connected to the other end of the second MOS transistor, the gate of which is controlled by a control signal. circuit means including a third MOS transistor having a shape, the other end being connected to the second potential supply end; one end being connected to the other end of the second MOS transistor and the other end being connected to the third potential supply end; a depletion type fourth MOS transistor whose gate is controlled by a signal having a logic level opposite to that of the control signal; When a higher potential is supplied than the second MOS transistor, the second MOS transistor is turned off by setting the signal at the opposite logic level to the logic level of the control signal to a low level. The current path from the potential supply terminal to the third potential supply terminal is cut off, and when the high potential is not supplied, the logic level of the control signal is set to a low level, and the fourth MOS
By turning on the transistor, a potential from the third potential supply end is supplied to the one end of the circuit means, and by turning the third MOS transistor off, a current is supplied to the circuit means. 2. A MOS transistor circuit, characterized in that the current path from the second potential supply terminal to the third potential supply terminal is cut off by preventing the current from flowing.