JPS62125713A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the power consumption in an input circuit by providing an input circuit having P/N-channel MOS transistors (TRs) connected in series and a voltage drop means so as to decrease the power voltage by a prescribed value and to supply the result to the input circuit thereby avoiding the external connection of a resistor. CONSTITUTION:The drain voltage of a MOS TR 21, that is, the power source voltage of a CMOS inverter 13 does not reach a value being the subtraction of a threshold voltage Vth21 from the gate voltage VG of the MOS TR 21. The voltage VG is a common voltage, then 0V, and in setting the voltage Vth21 to, e.g., -3V, in advance, the power source voltage of the CMOS inverter 13 does not reach 3V or above. Even when the threshold voltage of a P-channel MOS TR 11 is set to -1V, when the level '1' voltage of a signal CE is set to +2V or above, the TR 11 is turned off and no current is conducted to an inverter 13. Thus, the power consumption in the input circuit section is avoided without the connection of a resistor externally.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit with a complementary MO3 type configuration,
In particular, the present invention relates to a semiconductor integrated circuit that reduces power consumption in an input circuit section that receives external signals.

[Background of the technology of the invention] In general, semiconductor integrated circuits with a complementary MO8 type configuration (hereinafter referred to as CMOS) have low power consumption. It is characterized by its power properties, and has recently become particularly popular due to its low temperature and low power properties. FIG. 4 shows the configuration of a conventional input circuit section of such a CMOS semiconductor integrated circuit. This input circuit section is an input circuit section for an external signal, in particular, a chip enable signal σ for determining whether this semiconductor integrated circuit is in the vJ operating state or in the standby state.

The gates of a P-channel MOS transistor 11 and an N-channel MOS transistor 12 are connected to the input terminal 10 for the signal α. Both of the above M OS l
- The drains of the transistors 11 and 12 are connected in common, the source of the P-channel MOS transistor 11 is connected to the electric potential VC, and the source of the N-channel MOS transistor 12 is connected to the ground potential. A CMOS inverter 13 is configured to invert the signal α.

Furthermore, at the common drain connection point 14 of the MOS transistors 11 and 12, which becomes the output terminal of the inverter 13,
The gates of a P-channel MOS transistor 16 and an N-channel MOS transistor 17 constituting the next-stage CMOS inverter 15 are connected. CMO
As in the case of the S inverter 13, the drains of both MOS transistors 16 and 17 are connected in common, the source of the P channel MOS transistor 16 is connected to the power supply potential VC, and the source of the N channel Mo8 L-transistor 11 is connected to the ground. Each is connected to a potential. The signal at the common drain connection point 18 of the MOS transistors 16 and 17, which serves as the output terminal of the inverter 15, is then inverted by several stages of inverters and supplied to an internal control circuit (not shown). In addition, the above MOS
All transistors are of enhancement type, and the back gates of the P-channel and N-channel MOS transistors are connected to their respective sources.

In a semiconductor integrated circuit equipped with an input circuit section having such a configuration, the chip enable signal α is set to the "0" level to put it into the operating state, and the chip enable signal α is set to the "1" level to put it into the standby state. , power consumption is reduced during this standby state.

By the way, in the CMO8 semiconductor integrated circuit, in order to achieve response characteristics to external signals and stable DC operation, more specifically, in order to enable high-speed operation and operation with a lower power supply voltage, the internal P-channel The threshold voltages of the MOS transistor and the N-channel MOS l-transistor are set to about -1v and +1v, respectively.

[Problems with the frontal technology] By the way, the CMO8 semiconductor integrated circuit composed of MOS transistors with the threshold 1al pressure as described above is
When driven by an output signal from an L circuit or an N-channel MO3 type circuit, the 1' level of the above signal input as α is a voltage of about 2V to 3V. Therefore, when such a signal α is input to the input terminal 10 of the circuit shown in FIG. 4, the P-channel MOS transistor 11 and the N-channel Mo81 to transistor 12 are both turned on. Even during this bundling and standby, current flows between the power supply VC and the ground in the inverter 13 of the input circuit section, and power is consumed.

Therefore, in order to eliminate such power consumption, it has been conventionally possible to insert a pull-up resistor 19 between the power supply VC and the input terminal 10 outside the S integrated circuit, as shown by the broken line in FIG. It is being done. That is,
When a "1" level signal is input to the input terminal 10, the "1" level voltage is raised to the power supply VC, thereby turning off the P-channel MOS transistor 11 and eliminating power consumption in the input circuit section. be.

In this way, in the conventional system, in order to completely eliminate power consumption during standby, it is necessary to take the extra effort of connecting the resistor 19 externally, which has the disadvantage that the cost increases by the amount of the resistor 19. Note that in order to save the effort of externally attaching one of the above-mentioned resistors, it is conceivable to form the resistor in the integrated circuit from the beginning. However, connecting this resistor 19 causes leakage current at the input terminal. The value of leakage current at the input terminal varies depending on the user of the semiconductor integrated circuit. In addition, when connecting the terminals of multiple integrated circuits in common, one resistor is connected in parallel between the common connection and the power supply VC, which increases the leakage current depending on the number of integrated circuits used. The values will be different. For this reason, the value of the leakage current cannot be determined to be a specific value, and it is impossible to form the resistor 19 in advance in the integrated circuit.

[Object of the Invention] This invention has been made in consideration of the above circumstances, and its object is to provide a semiconductor integrated circuit that can eliminate power consumption in the input circuit section without connecting an external resistor. Our goal is to provide the following.

[Summary of the Invention] The present invention includes an input circuit having a P-channel and an N-channel Mo8I-transistor connected in series, to which an externally input signal is applied to each gate;
There has been provided a semiconductor integrated circuit characterized by comprising a voltage drop means inserted between the input circuit and the power supply to lower the power supply voltage by a predetermined value and supply the voltage to the input circuit.

“Embodiments of the invention” Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an input circuit section of a semiconductor integrated circuit according to an embodiment of the present invention. This embodiment circuit is a CMOS inverter 13 of the conventional circuit shown in FIG.
A new N-channel depletion type MOS transistor 21 is inserted between 1 and 1avc. The gate and back gate (portion that becomes a channel region) of this MOS transistor 21 are both connected to ground. Also, this MOS transistor 2
1 threshold (![1 pressure is set to -3V, for example.

In such a configuration, the MO8l-transistor 2
1, that is, the power supply voltage of the CMOS inverter 13, is the value obtained by subtracting the threshold voltage Vth21 from the gate voltage Va of the MOS transistor 21 (Va - V
th21) or higher. Here, Va is OV because it is the ground, and 2th21 is set to -3V in advance, so the power supply voltage of the CMOS inverter 13 does not exceed 3V. Therefore, this CMOS inverter 13
Even if the threshold voltage of the P-channel MOS transistor 11 is set to 11Vi, the P-channel MOS transistor 11 is turned off if the 1' level voltage of the signal α is +2V or more. Therefore, no current flows through this CMOS inverter 13. That is, since it is sufficient that the level voltage of the chip enable signal i'''i'' is +2V or higher, in a semiconductor integrated circuit equipped with this input circuit section,
Power consumption in the input circuit section can be eliminated even if it is driven by an output signal from a TTL circuit or an N-channel MO3 type circuit without connecting a resistor externally.

FIG. 2 is a circuit diagram showing the configuration of an input circuit section of a semiconductor integrated circuit according to another embodiment of the present invention.

In this example circuit, the depression type Mo81~
Instead of providing the transistor 21, two P-channel enhancement type MOS transistors 2 are connected in series between the CM OS inverter 13 and the power supply VC.
2 and 23 are inserted. The gates of both MOS l-transistors 22 and 23 are connected to their respective drains. Also, both M
The pressure of each of the OS transistors 22 and 23 is 11, similar to the P-channel MO8l-transistor.
It is set to v.

In this actual 11Mf94 circuit, when the power supply voltage VC is +5V, the power supply voltage of the CMOS inverter 13 is 5V.
V to P channel MO8I-Threshold 1a for 2 run rasters
It cannot exceed 3V, which is the sum of the ig pressure.

FIG. 3 is a circuit diagram showing a modification of the embodiment shown in FIG. 1 above. Here, the P channel MOS in the inverter 13
The back gate of the transistor 11 is not connected to its source, but is connected to the power supply VC. With such a connection, a sufficient back gate bias is applied to the P channel MOS transistor 11, so that the threshold ttmm pressure can be made smaller than -1V by the bank gate bias effect valve.

This makes it possible to perform D operation with a lower power supply voltage.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit that can eliminate power consumption in the input circuit section without externally connecting a resistor.

[Brief explanation of drawings]

1′! Figure 1 is a circuit diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a circuit diagram showing the configuration of another embodiment of this 51 light,
FIG. 3 is a circuit diagram showing a modification of the embodiment shown in FIG. 1, and FIG. 4 is a circuit diagram of a conventional circuit. 10...Input terminal, 11.16...M of P channel
OS transistor, 12.17...P channel MO
S transistor, 13.15...C to IOS inverter, 21...P channel depletion type MOS
Transistors 22, 23...P-channel enhancement type MOS i-transistors. Applicant's agent Patent attorney T Takehiko Suzue Figure 1C Figure 2

Claims (5)

[Claims] (1) An externally input signal is applied to each gate, and P-channel and N-channel MOs are connected in series.
1. A semiconductor integrated circuit comprising: an input circuit having an S transistor; and voltage drop means inserted between the input circuit and a power supply to lower the power supply voltage by a predetermined value and supply the voltage to the input circuit. . (2) The input circuit is a P-channel and N-channel MOS
The semiconductor integrated circuit according to claim 1, which is constituted by a complementary MOS type inverting circuit consisting of transistors. (3) The semiconductor integrated circuit according to claim 1, wherein the voltage drop means is constituted by a depletion type MOS transistor having a negative threshold voltage. (4) The semiconductor integrated circuit according to claim 3, wherein the gate of the MOS transistor is connected to a reference potential. (5) The semiconductor integrated circuit according to claim 1, wherein the voltage drop means is constituted by a plurality of enhancement type P-channel MOS transistors connected in series.