JPH02124634A - Four level output circuit - Google Patents

Four level output circuit

Info

Publication number
JPH02124634A
JPH02124634A JP63277912A JP27791288A JPH02124634A JP H02124634 A JPH02124634 A JP H02124634A JP 63277912 A JP63277912 A JP 63277912A JP 27791288 A JP27791288 A JP 27791288A JP H02124634 A JPH02124634 A JP H02124634A
Authority
JP
Japan
Prior art keywords
terminal
circuit
channel mosfet
vdd
connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63277912A
Inventor
Masami Hashimoto
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63277912A priority Critical patent/JPH02124634A/en
Publication of JPH02124634A publication Critical patent/JPH02124634A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To obtain a four level output circuit outputting 4 different potentials by using an output control circuit so as to apply ON/OFF control of 1st to 4th MOSFETs.
CONSTITUTION: An output control circuit 14 consists of a NAND circuit 21 and a NOR circuit 22 and an output terminal of the nOR circuit 22 is used as the 2nd output control terminal 19. Moreover, the 1st input terminal 16 and the 3rd output control terminal 20 are connected directly. A gate of a P-channel MOSFET 10 is connected to the 1st output control terminal 18, a gate of an N-channel MOSFET 11 is connected to the terminal 19 and gates of an N- channel MOSFET 12 and a P-channel MOSFET 13 are both connected to the terminal 20. Let a potential at a positive terminal +VDD be a potential VDD, the potential at a negative terminal -VSS be '0', a threshold voltage of the P-channel MOSFET be VTP, and the threshold voltage of the N-channel MOSFET be VTH, then the source of the MOSFET 10 is connected to the terminal +VDD, then a level VDD is outputted when the level of the gate is 0 and the MOSFET 10 is turned off when the gate level is VDD. Thus, the 4-value output circuit is constituted.
COPYRIGHT: (C)1990,JPO&Japio
JP63277912A 1988-11-02 1988-11-02 Four level output circuit Pending JPH02124634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63277912A JPH02124634A (en) 1988-11-02 1988-11-02 Four level output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63277912A JPH02124634A (en) 1988-11-02 1988-11-02 Four level output circuit

Publications (1)

Publication Number Publication Date
JPH02124634A true JPH02124634A (en) 1990-05-11

Family

ID=17590025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63277912A Pending JPH02124634A (en) 1988-11-02 1988-11-02 Four level output circuit

Country Status (1)

Country Link
JP (1) JPH02124634A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0459422A2 (en) * 1990-05-28 1991-12-04 Nec Corporation Data output circuit of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0459422A2 (en) * 1990-05-28 1991-12-04 Nec Corporation Data output circuit of semiconductor device
JPH0435224A (en) * 1990-05-28 1992-02-06 Nec Corp Semiconductor device
EP0459422A3 (en) * 1990-05-28 1994-05-04 Nec Corp

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