JPH01104567U - - Google Patents
Info
- Publication number
- JPH01104567U JPH01104567U JP20018787U JP20018787U JPH01104567U JP H01104567 U JPH01104567 U JP H01104567U JP 20018787 U JP20018787 U JP 20018787U JP 20018787 U JP20018787 U JP 20018787U JP H01104567 U JPH01104567 U JP H01104567U
- Authority
- JP
- Japan
- Prior art keywords
- logic gate
- signal line
- connection terminal
- input
- ttl
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Description
第１図は本考案の一実施例に係わる信号線接続
状態の検出回路の構成を接続端子ＩＮや外部信号
Ｓ線と共に示すブロツク図、第２図は第１図のＴ
ＴＬインバータの典型的な構成の一例を示す回路
図、第３図は第１図の検出回路の動作を説明する
ための真理値表である。
１……ＴＴＬインバータ、２ａ……トランジス
タ、３……検出結果の出力端子、ＩＮ……入力端
子、Ｓ……入力端子ＩＮに接続される外部信号線
。
FIG. 1 is a block diagram showing the configuration of a signal line connection state detection circuit according to an embodiment of the present invention together with a connection terminal IN and an external signal S line, and FIG.
A circuit diagram showing an example of a typical configuration of a TL inverter, and FIG. 3 is a truth table for explaining the operation of the detection circuit of FIG. 1. 1... TTL inverter, 2a... Transistor, 3... Output terminal of detection result, IN... Input terminal, S... External signal line connected to input terminal IN.
Claims (1)
るＴＴＬ論理ゲートと、 このＴＴＬ論理ゲートへの入力とこの論理ゲー
トからの出力とを受けそれぞれの二値状態の一致
、不一致に基づき前記接続端子に信号線が接続中
であるか否かを示す二値信号を出力する論理回路
とを備えたことを特徴とする信号線接続状態の検
出回路。[Claims for Utility Model Registration] A TTL logic gate having an input terminal connected to a connection terminal of a signal line, and an input to the TTL logic gate and an output from the logic gate, each of which has a corresponding binary state. and a logic circuit that outputs a binary signal indicating whether or not a signal line is connected to the connection terminal based on the mismatch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20018787U JPH01104567U (en) | 1987-12-29 | 1987-12-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20018787U JPH01104567U (en) | 1987-12-29 | 1987-12-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01104567U true JPH01104567U (en) | 1989-07-14 |
Family
ID=31699913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20018787U Pending JPH01104567U (en) | 1987-12-29 | 1987-12-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01104567U (en) |
-
1987
- 1987-12-29 JP JP20018787U patent/JPH01104567U/ja active Pending
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