JPS5888445U - Schmitt trigger circuit - Google Patents
Schmitt trigger circuitInfo
- Publication number
- JPS5888445U JPS5888445U JP18378281U JP18378281U JPS5888445U JP S5888445 U JPS5888445 U JP S5888445U JP 18378281 U JP18378281 U JP 18378281U JP 18378281 U JP18378281 U JP 18378281U JP S5888445 U JPS5888445 U JP S5888445U
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- mos
- trigger circuit
- schmitt trigger
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案の一実施例を示す電気的接続・図、第
２図は第１図の一部に関する動作説明図、第３図はその
入出力特性図、第４図は考案の原理を示す動作説明図、
第５図はその入出力特性曲線図、第６図は第１図に示す
実施例の入出力特性曲線図、第７図と第８図は本考案の
他の実施例を示す電気的接続図である。Fig. 1 is an electrical connection diagram showing one embodiment of the invention, Fig. 2 is an explanatory diagram of the operation of a part of Fig. 1, Fig. 3 is its input/output characteristic diagram, and Fig. 4 is an illustration of the invention. Operation diagram showing the principle,
Fig. 5 is an input/output characteristic curve diagram thereof, Fig. 6 is an input/output characteristic curve diagram of the embodiment shown in Fig. 1, and Figs. 7 and 8 are electrical connection diagrams showing other embodiments of the present invention. It is.
Claims (1)
インバータと、この第１のインバータのコモン側に互い
に並列に接続された２つのＭＯＳ−ＦＥＴと、前記第１
のインバータ出力をその入力信号とするＭＯＳ−ＦＥＴ
より構成された第２のインバータとを具備し、前記第２
のインバータの出力信号が前記互いに並列に接続された
２つのＭＯＳ−ＦＥＴの一方のＦＥＴのゲートに帰還さ
れ、これをオンオフさせることによりヒステリシスをも
たせるようにまたシュミット・トリガー回路。a first inverter composed of a MOS-FET that receives an input signal; two MOS-FETs connected in parallel to each other on the common side of the first inverter;
MOS-FET whose input signal is the inverter output of
and a second inverter configured from the second inverter.
The output signal of the inverter is fed back to the gate of one of the two MOS-FETs connected in parallel with each other, and the Schmitt trigger circuit is configured to provide hysteresis by turning it on and off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18378281U JPS5888445U (en) | 1981-12-10 | 1981-12-10 | Schmitt trigger circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18378281U JPS5888445U (en) | 1981-12-10 | 1981-12-10 | Schmitt trigger circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5888445U true JPS5888445U (en) | 1983-06-15 |
Family
ID=29983355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18378281U Pending JPS5888445U (en) | 1981-12-10 | 1981-12-10 | Schmitt trigger circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5888445U (en) |
-
1981
- 1981-12-10 JP JP18378281U patent/JPS5888445U/en active Pending
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