JPS63292647A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63292647A JPS63292647A JP62128862A JP12886287A JPS63292647A JP S63292647 A JPS63292647 A JP S63292647A JP 62128862 A JP62128862 A JP 62128862A JP 12886287 A JP12886287 A JP 12886287A JP S63292647 A JPS63292647 A JP S63292647A
- Authority
- JP
- Japan
- Prior art keywords
- series
- aluminum layer
- mosfets
- integrated circuit
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 230000005669 field effect Effects 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 27
- 229910052782 aluminium Inorganic materials 0.000 abstract description 27
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000009751 slip forming Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は大規模集積回路装置（ＬＳＩ）の構成の一部で
ある出力ドライ八回路に係り、特に電源ラインや信号ラ
イン等に発生するノイズを低減するための構造に関する
。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to eight output driver circuits that are part of the configuration of a large-scale integrated circuit device (LSI), and particularly relates to noise generated in power supply lines, signal lines, etc. Regarding a structure for reducing.
ＬＳＩにおいては１個の半導体チップ上に多数の回路素
子を形成して回路機能を持たせている。In an LSI, a large number of circuit elements are formed on one semiconductor chip to provide circuit functions.
ＬＳＩは、その内部に流れる信号の電流駆動能力が小さ
いので、他のチップあるいは外部機器へ信号を出力する
場合にはＬＳＩ内部に比べてチップ間あるいは外部機器
との間の距離が長く、減衰し易い。そこで通常ＬＳＩの
出力端側には出力ドライバを設けて電流駆動能力を大き
くしている。LSIs have a small current driving capacity for signals flowing inside them, so when outputting signals to other chips or external equipment, the distance between the chips or external equipment is longer than inside the LSI, resulting in attenuation. easy. Therefore, an output driver is usually provided on the output end side of the LSI to increase the current driving capability.
通常のゲートアレイ型ＬＳＩにおいては複数個のＭＯ５
型電界効果トランジスタ（ＭＯＳＦＥＴ）の出力を並列
に接続して出力ドライバを構成する。第４図（ａ）はそ
の−例を示す出力ドライバの回路構成のレイアウトパタ
ーンの平面図、第４図＜Ｃ）はその構成等価回路である
。同図において１はｎ型半導体基板中に形成されたｐ型
ウェル領域、２は該ウェル領域１中に形成されたｎ Ｍ
Ｏ８用の拡散領域、３は前記半導体基板中に形成され
たｐＭＯ３用の拡散領域、５４はポリシリコンゲ−１−
１５５は第１Ｎ目アルミニウム層、６は第２層目アルミ
ニウム層、５７は第１層目アルミニウム層５５−４とｐ
型つェル領域ｌとのコンタクト、５８は第１層目アルミ
ニウム層５５−２．５５−３と各拡散領域２．３とのコ
ンタクト、５９は第１層目アルミニウム層５５−４と電
源ライン６−１のコンタクト、６０は入力信号線である
第１Ｊ−目アルミニウム層５５−５とポリシリコンゲ−
）ｉ５４とのコンタクトを示す。In a normal gate array type LSI, multiple MO5
An output driver is configured by connecting the outputs of type field effect transistors (MOSFETs) in parallel. FIG. 4(a) is a plan view of a layout pattern of the circuit configuration of an output driver showing an example thereof, and FIG. 4<C) is an equivalent circuit of the configuration. In the figure, 1 is a p-type well region formed in an n-type semiconductor substrate, and 2 is an n-M well region formed in the well region 1.
A diffusion region for O8, 3 a diffusion region for pMO3 formed in the semiconductor substrate, 54 a polysilicon gate 1-
155 is the first N-th aluminum layer, 6 is the second aluminum layer, 57 is the first aluminum layer 55-4 and p
58 is a contact between the first aluminum layer 55-2, 55-3 and each diffusion region 2.3, 59 is a contact between the first aluminum layer 55-4 and the power supply line. Contact 6-1, 60 is the input signal line between the first J-th aluminum layer 55-5 and the polysilicon gate.
) indicates contact with i54.
第４図（ａ）においてｎ型半導体基板にはｐ−ウェル領
域１とその中に形成されたｎ Ｍ ＯＳ用の拡散領域２
とｐＭＯ３用の拡散領域３が形成され、デー１−酸化膜
（図示せず）を介して形成された各ポリソリコンゲート
５４によって第４図（Ｃ）にＮ１−Ｎ３として示すＮ−
ＭＯＳＦＥＴ及びＰ１〜Ｐ８として示すＰ−ＭＯＳＦＥ
Ｔが構成され、該基板上に眉間絶縁膜（図示せず）を用
いて多層配線を施してドライバ回路としている。即ち、
第１Ｍアルミニウム層５５で、ボンディングパソド５５
−１を含む出力信号線５５−２、電源ラインとのコンタ
クト形成層５５−３．５５−４、入力信号線５５−５を
形成し、第２層アルミニウム層６で電源ライン（Ｖｓｓ
ライン６−１、■ＤＤライン６−２）を形成する。In FIG. 4(a), an n-type semiconductor substrate has a p-well region 1 and a diffusion region 2 for an nMOS formed therein.
and pMO3 diffusion regions 3 are formed, and N-
MOSFETs and P-MOSFEs shown as P1-P8
A driver circuit is formed by providing multilayer wiring on the substrate using a glabella insulating film (not shown). That is,
In the first M aluminum layer 55, the bonding pad 55
-1, an output signal line 55-2 including contact formation layers 55-3 and 55-4 with the power supply line, and an input signal line 55-5 are formed, and the power supply line (Vss
line 6-1, DD line 6-2).
多層配線においては、第２層目アルミニウム層６を直接
半導体基板と接続出来ないので、例えばｐ−ウェル領域
１とＶｓｓライン６−１を接続する場合には第４図（ｂ
）に示す如く、基板Ｓ中に形成したｐ−ウェル領域１と
第１層目アルミニウム層５５−４にコンタクト５７を形
成して、この第１層目アルミニウム層５５−４とＶｓｓ
ライン６−１の間に眉間絶縁膜中にコンタクト５９を形
成して接続を完成させる。また第Ｉ層目アルミニウム層
５５と各拡散領域との接続も形成して第４図（Ｃ）に示
す構成等価回路が得られるように配線する。即ち、第４
図（ａ）に点線Ｐにより示すＰ−ＭＯＳＦＥＴについて
例示すると、入力信号は第１層アルミニウム線５５−５
とコンタクト６０からポリシリコンゲート５４に入力さ
れ、コンタクト５８により出力側信号線５５−２を通し
てボンディングパソド５５−１へ出力される。また５８
′は拡散領域３と第１層アルミニウム層５５−３とのコ
ンタクトを示し、コンタクト５９′を経て第２層アルミ
ニウム層（この場合ＶＤＤライン６−２）へ接続される
。他のＭＯＳＦＥＴも同様に接続され、結果的に第４図
（Ｃ）の等価回路を示ず如く、Ｐ１〜Ｐ８、Ｎ１〜Ｎ８
から成る相補型ＭＯ５ＦＥＴが並列に接続された構造と
なる。In multilayer wiring, since the second aluminum layer 6 cannot be directly connected to the semiconductor substrate, for example, when connecting the p-well region 1 and the Vss line 6-1, the method shown in FIG.
), a contact 57 is formed between the p-well region 1 formed in the substrate S and the first aluminum layer 55-4, and the first aluminum layer 55-4 and the Vss
A contact 59 is formed in the glabella insulating film between the lines 6-1 to complete the connection. Connections between the I-th aluminum layer 55 and each diffusion region are also formed and wired so as to obtain the equivalent circuit shown in FIG. 4(C). That is, the fourth
To illustrate the P-MOSFET shown by the dotted line P in Figure (a), the input signal is
is inputted to the polysilicon gate 54 from the contact 60, and outputted from the contact 58 to the bonding pad 55-1 through the output side signal line 55-2. Also 58
' denotes a contact between the diffusion region 3 and the first aluminum layer 55-3, which is connected to the second aluminum layer (in this case, the VDD line 6-2) via a contact 59'. Other MOSFETs are connected in the same way, and as a result, P1 to P8, N1 to N8, as shown in the equivalent circuit of FIG. 4(C).
It has a structure in which complementary MO5FETs consisting of are connected in parallel.
ところが、前記第４図に示したドライバ回路構成におい
ては各ＭＯ３ＦＥＴのポリシリコンゲート５４が並列に
、入力信号線である抵抗値の小さなアルミニウム層５５
−５によって接続されているので、第４図（ｃ）より明
らかなように、Ｐ−ＭＯＳＦＥＴ Ｐｉ〜Ｐ８のスイ
ッチングおよびＮ−ＭＯＳＦＥＴ Ｎ１〜Ｎ８のスイッ
チングはそれぞれほぼ同時に行われる。そのため信号が
入力された場合のスイッチングの際の過度電圧波形の立
上り、立下りの傾斜が急峻になり、これが電源ライン及
び信号ラインに大きな誘導ノイズを発生させる原因とな
るという問題点があった。However, in the driver circuit configuration shown in FIG.
-5, the switching of the P-MOSFETs Pi to P8 and the switching of the N-MOSFETs N1 to N8 are performed almost simultaneously, as is clear from FIG. 4(c). Therefore, there is a problem in that the rising and falling slopes of the transient voltage waveform during switching when a signal is input become steep, which causes large induced noise to be generated in the power supply line and the signal line.
従って本発明の目的は上記問題点を解決するためＬＳＩ
の出力ドライバの出力信号がゆっくり変化するような回
路構成の出力ドライバを提供するものである。Therefore, an object of the present invention is to solve the above problems by implementing an LSI
The present invention provides an output driver having a circuit configuration such that the output signal of the output driver changes slowly.
〔問題点を解決するための手段および作用〕ＬＳＩにお
ける相補型ＭＯＳ Ｆ ＥＴを用いた出力ドライバ回路
において、少なくとも２つ以上のＭＯＳＦＥＴのゲート
部分を直列接続する。[Means and operations for solving the problem] In an output driver circuit using complementary MOSFETs in an LSI, the gate portions of at least two MOSFETs are connected in series.
このように構成することにより、各ＭＯ３ＦＥＴとＭＯ
ＳＦＥＴの間のポリシリコンゲートとゲート酸化膜にお
ける浮遊容量とポリシリコン抵抗によって主に構成され
る遅延回路を各トランジスタの遅延素子として利用する
。この遅延回路は必ず各ＭＯＳ Ｆ ＥＴの人力段に形
成され、それによって各ＭＯＳ Ｆ ＥＴのスイッチン
グ開始時間が順次ずれて行き、かくして出力信号の立上
りがゆっくり変化するようになる。With this configuration, each MO3FET and MO
A delay circuit mainly composed of a polysilicon gate between SFETs, a stray capacitance in a gate oxide film, and a polysilicon resistor is used as a delay element of each transistor. This delay circuit is always formed in the manual stage of each MOS FET, so that the switching start time of each MOS FET is sequentially shifted, and thus the rise of the output signal changes slowly.
（１）第１実施例
本発明の一実施例を第１図及び第２図によって説明する
。(1) First Embodiment One embodiment of the present invention will be described with reference to FIGS. 1 and 2.
第１図（ａ）は本発明の出力ドライバのレイアウトパタ
ーンの一例の平面図、第１図（ｂ）はその等価回路図で
あり、第２図はこの実施例の基本原理説明図である。FIG. 1(a) is a plan view of an example of the layout pattern of the output driver of the present invention, FIG. 1(b) is an equivalent circuit diagram thereof, and FIG. 2 is a diagram illustrating the basic principle of this embodiment.
第１図において、１は半導体基板に形成されたｐ−ウェ
ル領域、２はｎ Ｍ ＯＳ用の拡散領域、３はｐＭＯ３
用の拡散領域、４はポリシリコンゲートで４′がその入
力４−ｒあり、５は第１層目アルミニウム層１．６は電
源ラインであり、６−１はＶｓｓライン、６−２はＶＤ
Ｄライン、７は第１層目アルミニウム層５とｐ−ウェル
領域１とのコンタ’／１−１８は第１層アルミニウム屓
５と各拡散領域２．３とのコンタクト、９は第１層目ア
ルミニウム層５と電源ライン６とのコンタクトを示す。In FIG. 1, 1 is a p-well region formed in a semiconductor substrate, 2 is a diffusion region for nMOS, and 3 is a pMO3
4 is the polysilicon gate, 4' is its input 4-r, 5 is the first aluminum layer 1.6 is the power supply line, 6-1 is the Vss line, 6-2 is the VD
D line, 7 is the contact between the first layer aluminum layer 5 and the p-well region 1; 1-18 is the contact between the first layer aluminum layer 5 and each diffusion region 2.3; 9 is the contact between the first layer aluminum layer 5 and each diffusion region 2.3; Contact between aluminum layer 5 and power supply line 6 is shown.
第１図（ａ）において半導体基板には第４図によって説
明した従来例と同様のｐ−ウェル領域１、ｎ Ｍ ＯＳ
用の拡散領域２、ｐＭＯ３用の拡散領域３が形成され、
ゲート酸化膜（図示せず）を介して形成されたポリシリ
コンゲート４によってＰ−ＭＯＳＦＥＴ Ｐｉ−Ｐ８
、Ｎ−ＭＯ３ＦＥＴＮ１〜Ｎ８が形成されており、この
半導体基板上には眉間絶縁膜（図示せず）を介して第１
層目アルミニウム層５、第２層目アルミニウム層６から
成る多層配線が施されている。即ち第１層目アルミニウ
ム層５はボンディングパソド５−１を含む出力側信号ラ
イン５−２、拡散層とのコンタクト形成層５−３．５−
４から成り、第２層目アルミニウムＮ６はＶｓ ｓライ
ン６−１、ＶＤＤライン６−２を構成している。In FIG. 1(a), the semiconductor substrate has a p-well region 1 similar to the conventional example explained in FIG.
A diffusion region 2 for pMO3 and a diffusion region 3 for pMO3 are formed,
A P-MOSFET Pi-P8 is formed by a polysilicon gate 4 formed through a gate oxide film (not shown).
, N-MO3FETN1 to N8 are formed on this semiconductor substrate through a glabella insulating film (not shown).
A multilayer wiring including a first aluminum layer 5 and a second aluminum layer 6 is provided. That is, the first aluminum layer 5 includes an output side signal line 5-2 including a bonding pad 5-1, and a contact formation layer 5-3.5- with a diffusion layer.
The second layer of aluminum N6 constitutes the Vss line 6-1 and the VDD line 6-2.
本実施例は第１図（ａ）から明らかな如く、各ＭＯ８Ｆ
ＥＴのゲートとなるポリシリコンが直列に連続して形成
されている。各拡散領域２．３とアルミニウム層５との
コンタクト８をポリシリコンゲート４の両側に設けるこ
とにより、第１図（ａ）の点線部分Ｐ、Ｐが１つのＰチ
ャネルＭＯ３ＦＥＴを形成する。１つのＦＥＴとその近
辺のポリシリコンゲート４によって等測的に第２図に示
す如く、ポリシリコンゲートと下層のゲート酸化膜によ
り形成される浮遊容量３４、とポリシリコンゲートの抵
抗３３によって遅延素子Ｂが′その入力側に形成された
ことになる。第１図（ａ）のパターンではこのような単
位がＰ−チ□ャネルＭ−Ｏ３ＦＥＴについて８個直列に
接続奢し、Ｎ−チャネルＭＯ３ＦＥＴについてこれまた
８個直列接゛続された構造となり、その等価回路図は第
１図’（ｔｔ）に示される如くになる。As is clear from FIG. 1(a), in this embodiment, each MO8F
Polysilicon that becomes the gate of the ET is formed continuously in series. By providing contacts 8 between each diffusion region 2.3 and the aluminum layer 5 on both sides of the polysilicon gate 4, the dotted line portions P and P in FIG. 1(a) form one P-channel MO3FET. As shown in FIG. 2, one FET and the polysilicon gate 4 in its vicinity form a delay element by the stray capacitance 34 formed by the polysilicon gate and the underlying gate oxide film, and the resistance 33 of the polysilicon gate. B is now formed on its input side. In the pattern of Fig. 1(a), eight such units are connected in series for P-channel M-O3FET, and eight such units are connected in series for N-channel MO3FET. The equivalent circuit diagram is shown in FIG. 1' (tt).
第１図（ｂ）において信号の入力から１つのＦＥ Ｔ
Ｐ ｎのスイッチングまでの遅延Ｔは、ＦＥＴＰｌの浮
遊容量とポリシリコンの抵抗による遅延時間Ｔ＋、ＦＥ
ＴＰ２の遅延時間Ｔ２−の和となるので（Ｔ＝ＴＩ ＋
Ｔ２ ＋−Ｔｎ）各ＦＥＴのスイッチングはＰｌあるい
はＮ１から一定の遅延間隔をおいて順次行われることに
なる。In Fig. 1(b), one FET is connected from the signal input.
The delay T until switching of Pn is the delay time T+ due to the stray capacitance of FET Pl and the resistance of polysilicon, FE
Since it is the sum of the delay time T2- of TP2, (T=TI +
T2 + - Tn) Switching of each FET is performed sequentially from Pl or N1 at a fixed delay interval.
従って、出力端に出力される信号波形の立上り立下りが
なだらかになり信号ライン、電源ラインへのノイズが低
減される。Therefore, the rising and falling edges of the signal waveform outputted to the output end are smooth, and noise to the signal line and power supply line is reduced.
（２） 第２実施例 第３図により本発明の他の実施例を説明する。(2) Second embodiment Another embodiment of the present invention will be explained with reference to FIG.
実際にポリシリコンゲートを多数直列に接続するや、と
により各Ｆ７Ｅ’Ｔのスイッチング開始時間をずらせて
出力信号を変化させる場合、遅延時間が長すぎると場合
によってスイッチングまでの時間が遅れすぎて信号に悪
影響を及ぼす。When actually connecting a large number of polysilicon gates in series, or changing the output signal by staggering the switching start time of each F7E'T, if the delay time is too long, the time until switching may be delayed too much, causing the signal to change. have a negative impact on
そこで第２実施−ではポリシリコンゲートをＮ−チャネ
ルＦＥＴ部分のポリシリコンゲート４０とＰ−ヂャネル
ＦＥＴ部分のポリシリコンゲート４１に分離し各ポリシ
リコンゲート４０．４１の両端にそれぞれ入力信号線で
ある第１層アルミニウム層５−５とのコンタクトＩＯを
設けた構造とする。Therefore, in the second implementation, the polysilicon gate is separated into a polysilicon gate 40 for the N-channel FET portion and a polysilicon gate 41 for the P-channel FET portion, and input signal lines are connected to both ends of each polysilicon gate 40 and 41, respectively. The structure includes a contact IO with the first aluminum layer 5-5.
この構造によってＰ−チャネルＦＥＴおよびＮ−チャネ
ルＦＥＴへの入力信号は二つのコンタクト１０．１０を
通して２個所より入力されるので全体としてのスイッチ
ングの遅延が第１実施例の場合の半分になる。With this structure, the input signals to the P-channel FET and N-channel FET are input from two places through the two contacts 10.10, so that the overall switching delay is half that of the first embodiment.
本発明の構成にすることによりＬＳＩの出力ドライバへ
の入力信号に対する各ＦＥＴのスイッチング開始を順次
遅延することが出来、従ってドライバの出力信号をゆっ
くり変化させることによって電源ライン、信号ラインに
発生するノイズレベルを低下することが出来る。By adopting the configuration of the present invention, it is possible to sequentially delay the start of switching of each FET in response to the input signal to the output driver of the LSI, and therefore, by slowly changing the output signal of the driver, noise generated in the power supply line and signal line can be reduced. You can lower the level.
また、直列に連続して配置するポリシリコンゲート層の
長さを短くして複数個所から同時に入力することにより
各トランジスタのスイッチングの遅延を短かくし、信号
波形を可変にすることも出来る。Furthermore, by shortening the length of the polysilicon gate layers arranged in series and simultaneously inputting signals from a plurality of locations, the switching delay of each transistor can be shortened and the signal waveform can be made variable.
第１図（ａ）は本発明の一実施例のレイアウトパターン
の平面図、
第１図（ｂ）はその等価回路図、
第２図は本発明の詳細な説明図、
第３図は他の実施例のレイアウトパターン、第４図（ａ
）は従来例のレイアウトパターンの平面図、
第４図（ｂ）はその配線状態説明図、
第４図（Ｃ）はその等価回路図である。
１ ＝Ｉｔ−ウェル領域
２−ｎ Ｍ ＯＳ用の拡散領域
３−ｐＭ Ｏ５用の拡散領域
４．４０．４１−ポリシリコンゲート
５−第１層アルミニウム層
６−第２層アルミニウム層FIG. 1(a) is a plan view of a layout pattern according to an embodiment of the present invention, FIG. 1(b) is an equivalent circuit diagram thereof, FIG. 2 is a detailed explanatory diagram of the present invention, and FIG. 3 is a plan view of a layout pattern of an embodiment of the present invention. Layout pattern of the example, Fig. 4 (a
) is a plan view of a conventional layout pattern, FIG. 4(b) is an explanatory diagram of its wiring state, and FIG. 4(C) is its equivalent circuit diagram. 1 = It-well region 2-n diffusion region for MOS 3-pMO5 diffusion region 4.40.41-polysilicon gate 5-first layer aluminum layer 6-second layer aluminum layer
Claims (3)
した出力ドライバを有するゲートアレイ集積回路におい
て、少なくとも２以上の電界効果トランジスタの入力信
号線に接続されたゲートを直列に接続した出力ドライバ
を具備したことを特徴とする半導体集積回路装置。(1) A gate array integrated circuit having an output driver in which the outputs of a plurality of field effect transistors are connected in parallel, including an output driver in which gates connected to input signal lines of at least two or more field effect transistors are connected in series. A semiconductor integrated circuit device characterized by:
特徴とする特許請求の範囲第１項記載の半導体集積回路
装置。(2) The semiconductor integrated circuit device according to claim 1, wherein the gate is made of polysilicon.
とＰチヤネル電界効果トランジスタ部とでそれぞれ連続
して直列接続したことを特徴とする特許請求の範囲第１
項記載の半導体集積回路装置。(3) The first aspect of the present invention is characterized in that the gates are connected in series in an N-channel field effect transistor section and a P-channel field effect transistor section, respectively.
The semiconductor integrated circuit device described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62128862A JPH0810759B2 (en) | 1987-05-26 | 1987-05-26 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62128862A JPH0810759B2 (en) | 1987-05-26 | 1987-05-26 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63292647A true JPS63292647A (en) | 1988-11-29 |
| JPH0810759B2 JPH0810759B2 (en) | 1996-01-31 |
Family
ID=14995208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62128862A Expired - Lifetime JPH0810759B2 (en) | 1987-05-26 | 1987-05-26 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810759B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01101650A (en) * | 1987-10-14 | 1989-04-19 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
| JPH01286614A (en) * | 1988-05-13 | 1989-11-17 | Ricoh Co Ltd | Output buffer circuit |
| JPH03135111A (en) * | 1989-10-20 | 1991-06-10 | Toshiba Micro Electron Kk | Output buffer circuit |
| EP0475757A2 (en) * | 1990-09-14 | 1992-03-18 | AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. | Integrated circuit having reduced sensitivity to voltage transients |
| JP2005277378A (en) * | 2004-02-24 | 2005-10-06 | Seiko Instruments Inc | High-voltage operation field effect transistor, its bias circuit and its high-voltage circuit |
| DE19541497B4 (en) * | 1994-11-11 | 2009-02-05 | Fuji Electric Co., Ltd., Kawasaki | Lateral field effect transistor |
| JP2012004581A (en) * | 2004-02-24 | 2012-01-05 | Seiko Instruments Inc | High-voltage operation method of field effect transistor and bias circuit thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5811258U (en) * | 1981-07-15 | 1983-01-25 | 日本電気株式会社 | integrated circuit |
-
1987
- 1987-05-26 JP JP62128862A patent/JPH0810759B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5811258U (en) * | 1981-07-15 | 1983-01-25 | 日本電気株式会社 | integrated circuit |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01101650A (en) * | 1987-10-14 | 1989-04-19 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
| JPH01286614A (en) * | 1988-05-13 | 1989-11-17 | Ricoh Co Ltd | Output buffer circuit |
| JPH03135111A (en) * | 1989-10-20 | 1991-06-10 | Toshiba Micro Electron Kk | Output buffer circuit |
| EP0475757A2 (en) * | 1990-09-14 | 1992-03-18 | AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. | Integrated circuit having reduced sensitivity to voltage transients |
| EP0475757B1 (en) * | 1990-09-14 | 1998-01-14 | NCR International, Inc. | Integrated circuit having reduced sensitivity to voltage transients |
| DE19541497B4 (en) * | 1994-11-11 | 2009-02-05 | Fuji Electric Co., Ltd., Kawasaki | Lateral field effect transistor |
| JP2005277378A (en) * | 2004-02-24 | 2005-10-06 | Seiko Instruments Inc | High-voltage operation field effect transistor, its bias circuit and its high-voltage circuit |
| JP2012004581A (en) * | 2004-02-24 | 2012-01-05 | Seiko Instruments Inc | High-voltage operation method of field effect transistor and bias circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0810759B2 (en) | 1996-01-31 |
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