JPS63292647A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS63292647A
JPS63292647A JP62128862A JP12886287A JPS63292647A JP S63292647 A JPS63292647 A JP S63292647A JP 62128862 A JP62128862 A JP 62128862A JP 12886287 A JP12886287 A JP 12886287A JP S63292647 A JPS63292647 A JP S63292647A
Authority
JP
Japan
Prior art keywords
series
aluminum layer
mosfets
integrated circuit
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62128862A
Other languages
Japanese (ja)
Other versions
JPH0810759B2 (en
Inventor
Hitoshi Ikeda
仁 池田
Shinjiro Toyoda
豊田 新次郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP62128862A priority Critical patent/JPH0810759B2/en
Publication of JPS63292647A publication Critical patent/JPS63292647A/en
Publication of JPH0810759B2 publication Critical patent/JPH0810759B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11803Masterslice integrated circuits using field effect technology
    • H01L27/11807CMOS gate arrays

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To change the rise-up of an output signal slowly, by connecting the gate parts of at least two or more MOSFETs in series, thereby sequentially shifting the switching starting time of each MOSFET. CONSTITUTION:Polysilicon parts, which are to become the gates of MOSFETs, are continuously formed in series. Contacts 8 for diffused regions 2 and 3 and an aluminum layer 5 are provided on both sides of a polysilicon gate 4. Dotted line parts P and P form one P-channel MOSFET. Eight units such as these are connected in series for the P-channel MOSFET. Eight units are connected in series also for N-channel MOSFETs. In this structure, switching of each FET is sequentially performed from P1 or N1 at a constant delay interval. Therefore, the rise-up and fall-down of a signal waveform, which is outputted from an output terminal become gentle, and noises to signal lines and power source lines are decreased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は大規模集積回路装置(LSI)の構成の一部で
ある出力ドライ八回路に係り、特に電源ラインや信号ラ
イン等に発生するノイズを低減するための構造に関する
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to eight output driver circuits that are part of the configuration of a large-scale integrated circuit device (LSI), and particularly relates to noise generated in power supply lines, signal lines, etc. Regarding a structure for reducing.

〔従来の技術〕[Conventional technology]

LSIにおいては1個の半導体チップ上に多数の回路素
子を形成して回路機能を持たせている。
In an LSI, a large number of circuit elements are formed on one semiconductor chip to provide circuit functions.

LSIは、その内部に流れる信号の電流駆動能力が小さ
いので、他のチップあるいは外部機器へ信号を出力する
場合にはLSI内部に比べてチップ間あるいは外部機器
との間の距離が長く、減衰し易い。そこで通常LSIの
出力端側には出力ドライバを設けて電流駆動能力を大き
くしている。
LSIs have a small current driving capacity for signals flowing inside them, so when outputting signals to other chips or external equipment, the distance between the chips or external equipment is longer than inside the LSI, resulting in attenuation. easy. Therefore, an output driver is usually provided on the output end side of the LSI to increase the current driving capability.

通常のゲートアレイ型LSIにおいては複数個のMO5
型電界効果トランジスタ(MOSFET)の出力を並列
に接続して出力ドライバを構成する。第4図(a)はそ
の−例を示す出力ドライバの回路構成のレイアウトパタ
ーンの平面図、第4図<C)はその構成等価回路である
。同図において1はn型半導体基板中に形成されたp型
ウェル領域、2は該ウェル領域1中に形成されたn M
 O8用の拡散領域、3は前記半導体基板中に形成され
たpMO3用の拡散領域、54はポリシリコンゲ−1−
155は第1N目アルミニウム層、6は第2層目アルミ
ニウム層、57は第1層目アルミニウム層55−4とp
型つェル領域lとのコンタクト、58は第1層目アルミ
ニウム層55−2.55−3と各拡散領域2.3とのコ
ンタクト、59は第1層目アルミニウム層55−4と電
源ライン6−1のコンタクト、60は入力信号線である
第1J−目アルミニウム層55−5とポリシリコンゲ−
)i54とのコンタクトを示す。
In a normal gate array type LSI, multiple MO5
An output driver is configured by connecting the outputs of type field effect transistors (MOSFETs) in parallel. FIG. 4(a) is a plan view of a layout pattern of the circuit configuration of an output driver showing an example thereof, and FIG. 4<C) is an equivalent circuit of the configuration. In the figure, 1 is a p-type well region formed in an n-type semiconductor substrate, and 2 is an n-M well region formed in the well region 1.
A diffusion region for O8, 3 a diffusion region for pMO3 formed in the semiconductor substrate, 54 a polysilicon gate 1-
155 is the first N-th aluminum layer, 6 is the second aluminum layer, 57 is the first aluminum layer 55-4 and p
58 is a contact between the first aluminum layer 55-2, 55-3 and each diffusion region 2.3, 59 is a contact between the first aluminum layer 55-4 and the power supply line. Contact 6-1, 60 is the input signal line between the first J-th aluminum layer 55-5 and the polysilicon gate.
) indicates contact with i54.

第4図(a)においてn型半導体基板にはp−ウェル領
域1とその中に形成されたn M OS用の拡散領域2
とpMO3用の拡散領域3が形成され、デー1−酸化膜
(図示せず)を介して形成された各ポリソリコンゲート
54によって第4図(C)にN1−N3として示すN−
MOSFET及びP1〜P8として示すP−MOSFE
Tが構成され、該基板上に眉間絶縁膜(図示せず)を用
いて多層配線を施してドライバ回路としている。即ち、
第1Mアルミニウム層55で、ボンディングパソド55
−1を含む出力信号線55−2、電源ラインとのコンタ
クト形成層55−3.55−4、入力信号線55−5を
形成し、第2層アルミニウム層6で電源ライン(Vss
ライン6−1、■DDライン6−2)を形成する。
In FIG. 4(a), an n-type semiconductor substrate has a p-well region 1 and a diffusion region 2 for an nMOS formed therein.
and pMO3 diffusion regions 3 are formed, and N-
MOSFETs and P-MOSFEs shown as P1-P8
A driver circuit is formed by providing multilayer wiring on the substrate using a glabella insulating film (not shown). That is,
In the first M aluminum layer 55, the bonding pad 55
-1, an output signal line 55-2 including contact formation layers 55-3 and 55-4 with the power supply line, and an input signal line 55-5 are formed, and the power supply line (Vss
line 6-1, DD line 6-2).

多層配線においては、第2層目アルミニウム層6を直接
半導体基板と接続出来ないので、例えばp−ウェル領域
1とVssライン6−1を接続する場合には第4図(b
)に示す如く、基板S中に形成したp−ウェル領域1と
第1層目アルミニウム層55−4にコンタクト57を形
成して、この第1層目アルミニウム層55−4とVss
ライン6−1の間に眉間絶縁膜中にコンタクト59を形
成して接続を完成させる。また第I層目アルミニウム層
55と各拡散領域との接続も形成して第4図(C)に示
す構成等価回路が得られるように配線する。即ち、第4
図(a)に点線Pにより示すP−MOSFETについて
例示すると、入力信号は第1層アルミニウム線55−5
とコンタクト60からポリシリコンゲート54に入力さ
れ、コンタクト58により出力側信号線55−2を通し
てボンディングパソド55−1へ出力される。また58
′は拡散領域3と第1層アルミニウム層55−3とのコ
ンタクトを示し、コンタクト59′を経て第2層アルミ
ニウム層(この場合VDDライン6−2)へ接続される
。他のMOSFETも同様に接続され、結果的に第4図
(C)の等価回路を示ず如く、P1〜P8、N1〜N8
から成る相補型MO5FETが並列に接続された構造と
なる。
In multilayer wiring, since the second aluminum layer 6 cannot be directly connected to the semiconductor substrate, for example, when connecting the p-well region 1 and the Vss line 6-1, the method shown in FIG.
), a contact 57 is formed between the p-well region 1 formed in the substrate S and the first aluminum layer 55-4, and the first aluminum layer 55-4 and the Vss
A contact 59 is formed in the glabella insulating film between the lines 6-1 to complete the connection. Connections between the I-th aluminum layer 55 and each diffusion region are also formed and wired so as to obtain the equivalent circuit shown in FIG. 4(C). That is, the fourth
To illustrate the P-MOSFET shown by the dotted line P in Figure (a), the input signal is
is inputted to the polysilicon gate 54 from the contact 60, and outputted from the contact 58 to the bonding pad 55-1 through the output side signal line 55-2. Also 58
' denotes a contact between the diffusion region 3 and the first aluminum layer 55-3, which is connected to the second aluminum layer (in this case, the VDD line 6-2) via a contact 59'. Other MOSFETs are connected in the same way, and as a result, P1 to P8, N1 to N8, as shown in the equivalent circuit of FIG. 4(C).
It has a structure in which complementary MO5FETs consisting of are connected in parallel.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが、前記第4図に示したドライバ回路構成におい
ては各MO3FETのポリシリコンゲート54が並列に
、入力信号線である抵抗値の小さなアルミニウム層55
−5によって接続されているので、第4図(c)より明
らかなように、P−MOSFET  Pi〜P8のスイ
ッチングおよびN−MOSFET N1〜N8のスイッ
チングはそれぞれほぼ同時に行われる。そのため信号が
入力された場合のスイッチングの際の過度電圧波形の立
上り、立下りの傾斜が急峻になり、これが電源ライン及
び信号ラインに大きな誘導ノイズを発生させる原因とな
るという問題点があった。
However, in the driver circuit configuration shown in FIG.
-5, the switching of the P-MOSFETs Pi to P8 and the switching of the N-MOSFETs N1 to N8 are performed almost simultaneously, as is clear from FIG. 4(c). Therefore, there is a problem in that the rising and falling slopes of the transient voltage waveform during switching when a signal is input become steep, which causes large induced noise to be generated in the power supply line and the signal line.

従って本発明の目的は上記問題点を解決するためLSI
の出力ドライバの出力信号がゆっくり変化するような回
路構成の出力ドライバを提供するものである。
Therefore, an object of the present invention is to solve the above problems by implementing an LSI
The present invention provides an output driver having a circuit configuration such that the output signal of the output driver changes slowly.

〔問題点を解決するための手段および作用〕LSIにお
ける相補型MOS F ETを用いた出力ドライバ回路
において、少なくとも2つ以上のMOSFETのゲート
部分を直列接続する。
[Means and operations for solving the problem] In an output driver circuit using complementary MOSFETs in an LSI, the gate portions of at least two MOSFETs are connected in series.

このように構成することにより、各MO3FETとMO
SFETの間のポリシリコンゲートとゲート酸化膜にお
ける浮遊容量とポリシリコン抵抗によって主に構成され
る遅延回路を各トランジスタの遅延素子として利用する
。この遅延回路は必ず各MOS F ETの人力段に形
成され、それによって各MOS F ETのスイッチン
グ開始時間が順次ずれて行き、かくして出力信号の立上
りがゆっくり変化するようになる。
With this configuration, each MO3FET and MO
A delay circuit mainly composed of a polysilicon gate between SFETs, a stray capacitance in a gate oxide film, and a polysilicon resistor is used as a delay element of each transistor. This delay circuit is always formed in the manual stage of each MOS FET, so that the switching start time of each MOS FET is sequentially shifted, and thus the rise of the output signal changes slowly.

〔実施例〕〔Example〕

(1)第1実施例 本発明の一実施例を第1図及び第2図によって説明する
(1) First Embodiment One embodiment of the present invention will be described with reference to FIGS. 1 and 2.

第1図(a)は本発明の出力ドライバのレイアウトパタ
ーンの一例の平面図、第1図(b)はその等価回路図で
あり、第2図はこの実施例の基本原理説明図である。
FIG. 1(a) is a plan view of an example of the layout pattern of the output driver of the present invention, FIG. 1(b) is an equivalent circuit diagram thereof, and FIG. 2 is a diagram illustrating the basic principle of this embodiment.

第1図において、1は半導体基板に形成されたp−ウェ
ル領域、2はn M OS用の拡散領域、3はpMO3
用の拡散領域、4はポリシリコンゲートで4′がその入
力4−rあり、5は第1層目アルミニウム層1.6は電
源ラインであり、6−1はVssライン、6−2はVD
Dライン、7は第1層目アルミニウム層5とp−ウェル
領域1とのコンタ’/1−18は第1層アルミニウム屓
5と各拡散領域2.3とのコンタクト、9は第1層目ア
ルミニウム層5と電源ライン6とのコンタクトを示す。
In FIG. 1, 1 is a p-well region formed in a semiconductor substrate, 2 is a diffusion region for nMOS, and 3 is a pMO3
4 is the polysilicon gate, 4' is its input 4-r, 5 is the first aluminum layer 1.6 is the power supply line, 6-1 is the Vss line, 6-2 is the VD
D line, 7 is the contact between the first layer aluminum layer 5 and the p-well region 1; 1-18 is the contact between the first layer aluminum layer 5 and each diffusion region 2.3; 9 is the contact between the first layer aluminum layer 5 and each diffusion region 2.3; Contact between aluminum layer 5 and power supply line 6 is shown.

第1図(a)において半導体基板には第4図によって説
明した従来例と同様のp−ウェル領域1、n M OS
用の拡散領域2、pMO3用の拡散領域3が形成され、
ゲート酸化膜(図示せず)を介して形成されたポリシリ
コンゲート4によってP−MOSFET  Pi−P8
、N−MO3FETN1〜N8が形成されており、この
半導体基板上には眉間絶縁膜(図示せず)を介して第1
層目アルミニウム層5、第2層目アルミニウム層6から
成る多層配線が施されている。即ち第1層目アルミニウ
ム層5はボンディングパソド5−1を含む出力側信号ラ
イン5−2、拡散層とのコンタクト形成層5−3.5−
4から成り、第2層目アルミニウムN6はVs sライ
ン6−1、VDDライン6−2を構成している。
In FIG. 1(a), the semiconductor substrate has a p-well region 1 similar to the conventional example explained in FIG.
A diffusion region 2 for pMO3 and a diffusion region 3 for pMO3 are formed,
A P-MOSFET Pi-P8 is formed by a polysilicon gate 4 formed through a gate oxide film (not shown).
, N-MO3FETN1 to N8 are formed on this semiconductor substrate through a glabella insulating film (not shown).
A multilayer wiring including a first aluminum layer 5 and a second aluminum layer 6 is provided. That is, the first aluminum layer 5 includes an output side signal line 5-2 including a bonding pad 5-1, and a contact formation layer 5-3.5- with a diffusion layer.
The second layer of aluminum N6 constitutes the Vss line 6-1 and the VDD line 6-2.

本実施例は第1図(a)から明らかな如く、各MO8F
ETのゲートとなるポリシリコンが直列に連続して形成
されている。各拡散領域2.3とアルミニウム層5との
コンタクト8をポリシリコンゲート4の両側に設けるこ
とにより、第1図(a)の点線部分P、Pが1つのPチ
ャネルMO3FETを形成する。1つのFETとその近
辺のポリシリコンゲート4によって等測的に第2図に示
す如く、ポリシリコンゲートと下層のゲート酸化膜によ
り形成される浮遊容量34、とポリシリコンゲートの抵
抗33によって遅延素子Bが′その入力側に形成された
ことになる。第1図(a)のパターンではこのような単
位がP−チ□ャネルM−O3FETについて8個直列に
接続奢し、N−チャネルMO3FETについてこれまた
8個直列接゛続された構造となり、その等価回路図は第
1図’(tt)に示される如くになる。
As is clear from FIG. 1(a), in this embodiment, each MO8F
Polysilicon that becomes the gate of the ET is formed continuously in series. By providing contacts 8 between each diffusion region 2.3 and the aluminum layer 5 on both sides of the polysilicon gate 4, the dotted line portions P and P in FIG. 1(a) form one P-channel MO3FET. As shown in FIG. 2, one FET and the polysilicon gate 4 in its vicinity form a delay element by the stray capacitance 34 formed by the polysilicon gate and the underlying gate oxide film, and the resistance 33 of the polysilicon gate. B is now formed on its input side. In the pattern of Fig. 1(a), eight such units are connected in series for P-channel M-O3FET, and eight such units are connected in series for N-channel MO3FET. The equivalent circuit diagram is shown in FIG. 1' (tt).

第1図(b)において信号の入力から1つのFE T 
P nのスイッチングまでの遅延Tは、FETPlの浮
遊容量とポリシリコンの抵抗による遅延時間T+、FE
TP2の遅延時間T2−の和となるので(T=TI +
T2 +−Tn)各FETのスイッチングはPlあるい
はN1から一定の遅延間隔をおいて順次行われることに
なる。
In Fig. 1(b), one FET is connected from the signal input.
The delay T until switching of Pn is the delay time T+ due to the stray capacitance of FET Pl and the resistance of polysilicon, FE
Since it is the sum of the delay time T2- of TP2, (T=TI +
T2 + - Tn) Switching of each FET is performed sequentially from Pl or N1 at a fixed delay interval.

従って、出力端に出力される信号波形の立上り立下りが
なだらかになり信号ライン、電源ラインへのノイズが低
減される。
Therefore, the rising and falling edges of the signal waveform outputted to the output end are smooth, and noise to the signal line and power supply line is reduced.

(2)  第2実施例 第3図により本発明の他の実施例を説明する。(2) Second embodiment Another embodiment of the present invention will be explained with reference to FIG.

実際にポリシリコンゲートを多数直列に接続するや、と
により各F7E’Tのスイッチング開始時間をずらせて
出力信号を変化させる場合、遅延時間が長すぎると場合
によってスイッチングまでの時間が遅れすぎて信号に悪
影響を及ぼす。
When actually connecting a large number of polysilicon gates in series, or changing the output signal by staggering the switching start time of each F7E'T, if the delay time is too long, the time until switching may be delayed too much, causing the signal to change. have a negative impact on

そこで第2実施−ではポリシリコンゲートをN−チャネ
ルFET部分のポリシリコンゲート40とP−ヂャネル
FET部分のポリシリコンゲート41に分離し各ポリシ
リコンゲート40.41の両端にそれぞれ入力信号線で
ある第1層アルミニウム層5−5とのコンタクトIOを
設けた構造とする。
Therefore, in the second implementation, the polysilicon gate is separated into a polysilicon gate 40 for the N-channel FET portion and a polysilicon gate 41 for the P-channel FET portion, and input signal lines are connected to both ends of each polysilicon gate 40 and 41, respectively. The structure includes a contact IO with the first aluminum layer 5-5.

この構造によってP−チャネルFETおよびN−チャネ
ルFETへの入力信号は二つのコンタクト10.10を
通して2個所より入力されるので全体としてのスイッチ
ングの遅延が第1実施例の場合の半分になる。
With this structure, the input signals to the P-channel FET and N-channel FET are input from two places through the two contacts 10.10, so that the overall switching delay is half that of the first embodiment.

〔発明の効果〕〔Effect of the invention〕

本発明の構成にすることによりLSIの出力ドライバへ
の入力信号に対する各FETのスイッチング開始を順次
遅延することが出来、従ってドライバの出力信号をゆっ
くり変化させることによって電源ライン、信号ラインに
発生するノイズレベルを低下することが出来る。
By adopting the configuration of the present invention, it is possible to sequentially delay the start of switching of each FET in response to the input signal to the output driver of the LSI, and therefore, by slowly changing the output signal of the driver, noise generated in the power supply line and signal line can be reduced. You can lower the level.

また、直列に連続して配置するポリシリコンゲート層の
長さを短くして複数個所から同時に入力することにより
各トランジスタのスイッチングの遅延を短かくし、信号
波形を可変にすることも出来る。
Furthermore, by shortening the length of the polysilicon gate layers arranged in series and simultaneously inputting signals from a plurality of locations, the switching delay of each transistor can be shortened and the signal waveform can be made variable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は本発明の一実施例のレイアウトパターン
の平面図、 第1図(b)はその等価回路図、 第2図は本発明の詳細な説明図、 第3図は他の実施例のレイアウトパターン、第4図(a
)は従来例のレイアウトパターンの平面図、 第4図(b)はその配線状態説明図、 第4図(C)はその等価回路図である。 1 =It−ウェル領域 2−n M OS用の拡散領域 3−pM O5用の拡散領域 4.40.41−ポリシリコンゲート 5−第1層アルミニウム層 6−第2層アルミニウム層
FIG. 1(a) is a plan view of a layout pattern according to an embodiment of the present invention, FIG. 1(b) is an equivalent circuit diagram thereof, FIG. 2 is a detailed explanatory diagram of the present invention, and FIG. 3 is a plan view of a layout pattern of an embodiment of the present invention. Layout pattern of the example, Fig. 4 (a
) is a plan view of a conventional layout pattern, FIG. 4(b) is an explanatory diagram of its wiring state, and FIG. 4(C) is its equivalent circuit diagram. 1 = It-well region 2-n diffusion region for MOS 3-pMO5 diffusion region 4.40.41-polysilicon gate 5-first layer aluminum layer 6-second layer aluminum layer

Claims (3)

【特許請求の範囲】[Claims] (1)複数の電界効果トランジスタの出力を並列に接続
した出力ドライバを有するゲートアレイ集積回路におい
て、少なくとも2以上の電界効果トランジスタの入力信
号線に接続されたゲートを直列に接続した出力ドライバ
を具備したことを特徴とする半導体集積回路装置。
(1) A gate array integrated circuit having an output driver in which the outputs of a plurality of field effect transistors are connected in parallel, including an output driver in which gates connected to input signal lines of at least two or more field effect transistors are connected in series. A semiconductor integrated circuit device characterized by:
(2)前記ゲートをポリシリコンにより構成したことを
特徴とする特許請求の範囲第1項記載の半導体集積回路
装置。
(2) The semiconductor integrated circuit device according to claim 1, wherein the gate is made of polysilicon.
(3)前記ゲートをNチヤネル電界効果トランジスタ部
とPチヤネル電界効果トランジスタ部とでそれぞれ連続
して直列接続したことを特徴とする特許請求の範囲第1
項記載の半導体集積回路装置。
(3) The first aspect of the present invention is characterized in that the gates are connected in series in an N-channel field effect transistor section and a P-channel field effect transistor section, respectively.
The semiconductor integrated circuit device described in .
JP62128862A 1987-05-26 1987-05-26 Semiconductor integrated circuit device Expired - Lifetime JPH0810759B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62128862A JPH0810759B2 (en) 1987-05-26 1987-05-26 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62128862A JPH0810759B2 (en) 1987-05-26 1987-05-26 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS63292647A true JPS63292647A (en) 1988-11-29
JPH0810759B2 JPH0810759B2 (en) 1996-01-31

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP62128862A Expired - Lifetime JPH0810759B2 (en) 1987-05-26 1987-05-26 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0810759B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01101650A (en) * 1987-10-14 1989-04-19 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device
JPH01286614A (en) * 1988-05-13 1989-11-17 Ricoh Co Ltd Output buffer circuit
JPH03135111A (en) * 1989-10-20 1991-06-10 Toshiba Micro Electron Kk Output buffer circuit
EP0475757A2 (en) * 1990-09-14 1992-03-18 AT&amp;T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. Integrated circuit having reduced sensitivity to voltage transients
JP2005277378A (en) * 2004-02-24 2005-10-06 Seiko Instruments Inc High-voltage operation field effect transistor, its bias circuit and its high-voltage circuit
DE19541497B4 (en) * 1994-11-11 2009-02-05 Fuji Electric Co., Ltd., Kawasaki Lateral field effect transistor
JP2012004581A (en) * 2004-02-24 2012-01-05 Seiko Instruments Inc High-voltage operation method of field effect transistor and bias circuit thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5811258U (en) * 1981-07-15 1983-01-25 日本電気株式会社 integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5811258U (en) * 1981-07-15 1983-01-25 日本電気株式会社 integrated circuit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01101650A (en) * 1987-10-14 1989-04-19 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device
JPH01286614A (en) * 1988-05-13 1989-11-17 Ricoh Co Ltd Output buffer circuit
JPH03135111A (en) * 1989-10-20 1991-06-10 Toshiba Micro Electron Kk Output buffer circuit
EP0475757A2 (en) * 1990-09-14 1992-03-18 AT&amp;T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. Integrated circuit having reduced sensitivity to voltage transients
EP0475757B1 (en) * 1990-09-14 1998-01-14 NCR International, Inc. Integrated circuit having reduced sensitivity to voltage transients
DE19541497B4 (en) * 1994-11-11 2009-02-05 Fuji Electric Co., Ltd., Kawasaki Lateral field effect transistor
JP2005277378A (en) * 2004-02-24 2005-10-06 Seiko Instruments Inc High-voltage operation field effect transistor, its bias circuit and its high-voltage circuit
JP2012004581A (en) * 2004-02-24 2012-01-05 Seiko Instruments Inc High-voltage operation method of field effect transistor and bias circuit thereof

Also Published As

Publication number Publication date
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