JPH01286614A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To suppress the generation of the noise at the time of switching by serially connecting plural FETs for pull-down to an FET for a buffer, and connecting a CR circuit to each gate of the FET for pull-down. CONSTITUTION:When an 'H' level is inputted to an input terminal I, FETQ0 and Q1 are turned on, and a current I1 is applied through the FETQ1 to the FETQ0. Next, after a time constant determined by a resistance R1 and a capacitor C1, the FETQ2 is turned on, and a current I2 is applied to the FETQ2 as well. Further, when the time constant determined by a resistance R2 and a capacitor C2 passes, an FETQ3 is also turned on, a current I3 is applied to the FETQ3, successively, after the time constant determined by a resistance R3 and a capacitor C3, a FETQ4 is also turned on, and a current I4 is applied to the FETQ4. In such a way, since the current to increase in stages according to the passage of the time is applied, the sharp current change is not generated, and the noise generation at the time of the switching can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit in an integrated circuit.

[Prior Art] Conventionally, in order to increase the drive capability of an output buffer, the output buffer is constructed using a large-sized, ie, high-output FET (field effect transistor).

[Problems to be Solved by the Invention] As a result, a large current is intermittent as the FET is turned on and off, which causes noise during switching, causing the integrated circuit to malfunction.

The present invention has been made to eliminate the above-mentioned problems, and an object thereof is to provide an output buffer circuit that suppresses noise generation.

[Means for Solving the Problems] The output buffer circuit of the present invention connects a plurality of pull-down FETs whose sources and drains are interconnected in series with a buffer FET, and
When the pull-down FET is turned on, the pull-down FET is turned on sequentially after a predetermined timing.
It is characterized in that a CR circuit is connected to each gate of the T.

[Operation] According to the above configuration, when the buffer PET is turned on, the CR circuit connected to each gate of the pull-down FET is turned on sequentially according to the time constant, so that the buffer FET is turned on in sequence according to the time constant.
The current flowing through the ET gradually increases over time.

[Embodiment] FIG. 1 shows an embodiment of the output buffer circuit of the present invention.

An output PET Qo is connected between the 10 line L and the output terminal 0, and pull-down FETs Q and -Q are connected between the output terminal 0 and the ground 8, respectively.

The input terminal ■ is connected to the input part of the buffer B2, and is also connected to the input terminal of the buffer B! through the inverter INV. connected to the input section of the The output part of the buffer Bl is FET
Q Connected to the gate of o. The output part of buffer B2 is connected to the gate of FETQ, and is connected to the resistor R,
is connected to the gate of FETQt via.

The gate of FE T Q t is connected to FE through resistor R2.
It is connected to the gate of FETQ3, and the gate of FETQs is connected to the gate of FETQ4 via a resistor R8.

In addition, capacitors C1 and Cs are connected between the gates of FETQt, Qs, and Q4 and the ground 8, respectively.
, Cs are connected.

The size of FETQo is the normal size 9
00/3.5, and F'ETQ,,Qt,Q,,Q,
The sizes are 50/3.5 and 100/3.5, respectively.
゜150/3.5, 200/3.5, and the ratio is 1:
They increase in the order of 2:3:4.

In operation, when the "H" level is input to the input terminal ■, the FETQ is
O is turned on and FETQ is turned on by buffer B2.
, is turned on, p”ETQo is turned on via FETQ,
Current ■1 flows through. Current at this time 1. The size of
It is proportional to the size of F'ETQ, 50/3.5.

Next, the time constant τ1 determined by the resistor R5 and the capacitor CI
Later, F E T Q * is turned on, and F E T Q
! Also electric current! , starts to flow. This current l is proportional to the size 100/3.5 of the FETQ*, so It=211.

Furthermore, the time constant τ determined by the resistor R and the capacitor C1,
When , F ET Q s also turns on, r 5 (-a ■,) flows into the F ET Q 3, and then, after a time constant τ4 determined by resistor R8 and capacitor C3, PET Q also turns on. Then, the current in the FETQ is 14
(-411) flows.

Therefore, for FETQo, Il+I, +Ibar=31
1), I, +1. + 13 (=610.!, +
I, +1, +14 (= 1010), since a current that increases step by step with the passage of time flows, no sudden current changes occur, and therefore the generation of noise is suppressed.

FIG. 2 shows an example of a layout on an integrated circuit for the circuit of FIG. Q,,Qt.

Q, ,Q, are each of the above FETs, and X is a contact, which corresponds to the line L above. Y is a diffusion portion where impurities are diffused.

[Effects of the Invention] As explained above, according to this invention, the buffer P
Since the current flowing through ET was gradually increased,
Noise generation caused by rapid current changes is suppressed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an output buffer circuit of the present invention, and FIG. 2 is a diagram showing an example of a layout when the circuit of FIG. 1 is integrated. Bl, B2...Buffer, Q, , Q, or Q4 FET. R1 or R1...Resistor, C, or C3...Capacitor.

Claims (1)

[Claims] (1) Connect multiple pull-down FETs with their sources and drains interconnected in series with the buffer FET, and when the buffer FET turns on, the pull-down FETs turn on one after another after a predetermined timing. An output buffer characterized in that a CR circuit is connected to each gate of the pull-down FET.