JPH03157011A - Level conversion circuit and delay circuit using the same level conversion circuit - Google Patents

Abstract

PURPOSE:To decrease the area occupied by an IC chip in the case of circuit integration by employing a single power supply and obtaining an output signal converted into an optional voltage. CONSTITUTION:Transistors(TRs) TP11, TN11 constitute an inverter provided between a power supply VDD and ground GND and an input signal IN1 is fed to the input. Moreover, TRs TP12, TN12 are connected in series between the power supply VDD and ground GND and an output OUT1 subject to level conversion is outputted from the connection between the TRs TP12, TN12. Thus, the single power supply VDD is in use to obtain a converted output signal OUT1 into an optional voltage (optional voltage lower than the voltage of the power supply VDD).

Description

Detailed Description of the Invention: ``Summary'' Regarding a level converter circuit configured using MOS transistors, this can be integrated into an IC by using a single power supply to obtain an output signal converted to an arbitrary voltage. In order to reduce the area occupied by the IC chip by minimizing the number of pads on the IC chip, a level conversion circuit converts an input signal to extract an output signal of a predetermined level, and a first MOS transistor of one conductivity type, which is provided between an inverter to which an input signal is supplied, a signal line for taking out the output signal, and a power supply, and whose gate is supplied with the output of the inverter; a second transistor of a conductivity type opposite to that of the first transistor, which is provided between the transistor and the ground and whose gate is supplied with the input signal;
an OS transistor, and a third MOS transistor of an opposite conductivity type, which is provided between the signal line and ground and whose gate is supplied with the output of the inverter, and which is connected to the first and second MOS transistors by the input signal. Both transistors are turned on, and an output signal of an arbitrary voltage lower than the voltage of the power source is extracted depending on the ratio of the on-resistances of the first and second transistors.

[Industrial Field of Application] The present invention relates to a level conversion circuit and a delay circuit using the level conversion circuit, more specifically, a level conversion circuit configured using MOS transistors and a delay circuit using the level conversion circuit. This invention relates to a delay circuit.

[Prior Art] FIG. 9 is a circuit diagram showing an example of a conventional level conversion circuit. As shown in the figure, the conventional level conversion circuit is
For example, P-type MOS transistor TPo1 and N-type M
A first inverter composed of an OS transistor TNo, a P-type MO3 transistor TP, 2, and an N-type MO3
A second inverter configured with an S transistor TNO2 is provided, and the output of the first inverter is supplied to the input of the second inverter. Here, a first power source ■DD1 is applied to the first inverter, and a second power source voo2 having a voltage different from the first power source Voot is applied to the second inverter. .

and an output 0 which is inverted from the output of the first inverter.
UTo is taken out, and level-converted 0tJTO is taken out from the output of the second inverter.

[Problems to be Solved by the Invention] The conventional level conversion circuit shown in FIG. Power supplies of different voltages, i.e. voltages corresponding to the required level (e.g.
A second power source VoD2) had to be prepared.

FIG. 10 is a block diagram schematically showing an example of a device to which a conventional level conversion circuit is applied, and in the figure, reference symbols A1, A2, and A3 are level conversion circuits.

As shown in FIG. 10, for example, in response to the output of the 50V drive IC, the 5V drive IC1IOV drive rc and 2
Level conversion circuit A1 converts a 50V level input signal to a 5V level in an IC (level conversion IC) that converts a level to be suitable for a 0V drive IC.Converts a 50V level input signal to an IOV level. The level conversion circuit A2 and the level conversion circuit A3, which converts an input signal at a level of 50V to a level of 20V, are each supplied with power at a voltage suitable for the output level.

In other words, level conversion circuit A! A 5V power supply is supplied to the level conversion circuit A2, an IOV power supply is supplied to the level conversion circuit A2, and a 20V power supply is supplied to the level conversion circuit A2. Therefore, the level conversion IC must be provided with terminals for each power source (5V power supply, IOV power supply, and 20V power supply), which increases the number of pads within the level conversion IC and increases the area occupied by the IC chip. There was a problem.

Furthermore, a delay circuit as shown in FIG. 1X has been proposed in the past.

In the figure, 11 is a delayed signal input terminal to which a delayed signal is manually input, and 12 is a delayed signal output terminal to which a delayed signal is output.
and the delay signal output terminal 12, a P-type MO3 transistor TP3. and an inverter I31 consisting of an N-type MOI-transistor TN, and a P-type MO3 transistor T.
An inverter I3□ consisting of P, 2 and N type MOS transistors TNS2 and an inverter 133 consisting of a P type MO3 transistor TP33 and an N type MO3 transistor TN are connected in series, and the final stage inverter I3'l is connected to a power source Vof. ) is supplied as the power supply voltage, and the first and second stage inverters L31.1, 2 are configured to supply the voltage of the power supply Va (however, the voltage of the power supply Va (the voltage of the power supply VDt)). ing.

Here, in general, when the power supply voltage of an inverter is lowered, its delay time is increased. Therefore, according to such a conventional delay circuit, although it is possible to obtain a delay signal whose maximum voltage is the same voltage as the voltage of the power supply VDD,
A larger delay time can be obtained compared to a delay circuit that supplies the voltage of the power supply VDD as the power supply voltage to all the inverters I31, I3□, and In2. That is,
A larger delay time can be obtained with fewer stages of inverters.

However, such conventional delay circuits require two types of voltages as power supply voltages: the voltage of the power supply DD and the voltage of the power supply Va.
In addition to the external terminal for power supply VDD,
An external terminal for the power supply Va is required, which results in an increase in the number of IC pads and a problem in that the area occupied by the IC chip increases.

In view of this, the present invention uses a single power supply to obtain an output signal converted to an arbitrary voltage, thereby minimizing the number of pads on the IC chip when converting it into an IC. When using this level conversion circuit and converting it into an IC, the number of pads on the IC chip can be reduced to reduce the area occupied by the IC chip. The object of the present invention is to provide a delay circuit that can occupy a small area.

[Means for Solving the Problems] FIG. 1 is a circuit diagram showing the principle of a level conversion circuit according to the present invention.

The level conversion circuit according to the present invention is a level conversion circuit that converts an input signal IN1 to obtain an output signal OUT of a predetermined level, and includes an inverter (2) to which the input signal IN is supplied, and an output signal 0 (JT, A first MOS transistor T of one conductivity type is provided between the signal line SL for taking out the signal and the power supply VbD, and the output of the inverter I is supplied to the gate.
P, 2, provided between the signal line SL and the ground GND,
A second MOS transistor T having a conductivity type opposite to that of the first transistor TP1□ whose gate is supplied with an input signal IN.
N12, provided between the signal line SL and the ground GND,
A third MOS transistor TN, 3 of an opposite conductivity type whose gate is supplied with the output of the inverter I, and the first and second MOS transistors T are provided with an input signal IN.
P, 23, TN, 2 are both in the on state, and these first
According to the ratio of the on-resistances of the second M○S transistor TP123TN12, the output signal OUT of an arbitrary voltage lower than the voltage of the power supply (2)oD is output.

FIG. 2 is a circuit diagram showing the principle of the delay circuit according to the present invention.

The delay circuit according to the present invention includes a plurality of inverters connected in series, for example, three inverters 131.13231.
33 and the level conversion circuit 13 according to the present invention, and among these three inverters 131, 132, and I33, at least one inverter of the inverters I3L and h2 other than the final stage inverter rsx, for example, the first stage and the second stage The inverters r3t and I32 in the second stage have a second voltage which is obtained at the output terminal 15 when a first voltage, for example, the voltage of the power supply ■DD, is supplied to the input terminal 14 of the level conversion circuit 13 according to the present invention. For example, the voltage of the power supply VDD is supplied to an inverter other than the inverter that supplies the same voltage as the voltage of the power supply Va, for example, the final stage inverter h3. is configured to supply as the power supply voltage.

C Effect: According to the level conversion circuit of the present invention, the signal line SL for taking out the output signal out'rt in response to the input signal INI and the power supply ■
First MOS transistor TP1□ provided between DD
and a second M provided between the signal line SL and the ground GND.
Both the OS transistors TN, 2 are turned on, and the first and second MOS transistors TP, □.

T.N. The output signal OUT 1 of an arbitrary voltage lower than the voltage of the power source Voo is taken out depending on the ratio of the on-resistances. Here, the third MOS transistor TN is turned on when the output signal 0UTl is set to a low level, and is used to output the level of the ground GND as the output signal 0UT1.

As described above, according to the level conversion circuit of the present invention, an output signal converted to an arbitrary voltage is obtained using a single power supply, so when converting this into an IC, it is necessary to By minimizing the number of IC chips, the area occupied by the IC chip can be kept small.

Further, according to the delay circuit of the present invention, at least one inverter among the cascade-connected inverters 131, I3□, 133, for example, two inverters I31.
For example, the same voltage as the voltage of the power supply Va is supplied as the power supply voltage to the final stage inverter 1.2. ．． 3 is supplied with the voltage of the power supply VDo,
Since the level conversion circuit according to the present invention is used, when it is integrated into an IC, it is sufficient to provide an external terminal for the power source VDD, and there is no need to provide an external terminal for the power source Va.

Therefore, according to the delay circuit of the present invention, when it is integrated into an IC, the number of pads on the IC chip can be reduced and the I
The area occupied by the C chip can be kept small.

[Embodiments] Hereinafter, embodiments of a level conversion circuit and a delay circuit according to the present invention will be described with reference to the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the level conversion circuit of the present invention. As shown in the figure, the level conversion circuit of this embodiment includes P-type MOS transistors TPI□, TP, □
and an N-type MOS transistor TN.

TN】23 Consists of TN, 3. Transistors TP, □, and TN1□ constitute an inverter provided between the power supply Vpp and the ground GND, and the input signal IN is input to the inverter.

is supplied. Further, transistors TP, □ and TN, 2 are connected in series between the power supply VDD and the ground GND, and the connection points between these transistors TP, □ and TN, 2 (node n1 □, signal line SL for taking out the output signal) )
The level-converted output 0UT1 is outputted from the output 0UT1. Here, the input signal IN is also supplied to the gate of the transistor TN12, and the output (node n1□) of the inverter composed of the transistors TP11 and TNl is set to the inverted output 0 (JTl), and It is supplied to the gates of transistors TP, □ and TNl.

4 and 5 are equivalent circuit diagrams for explaining the operation of the level conversion circuit shown in FIG. 3, and FIG. 3 shows the input signal I
FIG. 5 shows the case where the input signal IN is at the low level "L".

First, as shown in FIG. 4, in the level conversion circuit of FIG. 3, when the input signal INl is at a high level "H", the transistor TpH is switched off, and the transistor TN, □
, TN,2 is switched on. As a result, the node n1 (inverted output OUT+) is at a low level "L"
Therefore, the transistor TP12 is switched on and the transistor TNI3 is switched off.

Therefore, the node n+2 (signal line SL from which the output signal OUT is taken out) has a voltage level divided by the on-resistance of the transistor TP12 and the on-resistance of the transistor TN. That is, by manufacturing the transistors TP, □ and TN, 2 so that the on-resistance ratio of the transistors becomes a predetermined value, the level of the output signal OUT+ can be set to an arbitrary voltage lower than the voltage of the power supply VD+:1. level (0<output voltage<Voo).

Next, as shown in FIG. 5, when the input signal IN is at a low level "L" in the level conversion circuit of FIG.
, TNl2 is switched off. As a result, the node n1□ becomes high level "'H", and the transistor T
P12 is switched off and transistor TN,3 is switched on. Therefore, the node n12 is brought to the ground potential by the transistor TN,3.

In this way, the level conversion circuit of this embodiment has a single power supply V
Using Dp, it is possible to obtain an output signal 0UT1 converted to an arbitrary voltage (any voltage lower than the voltage of the power supply V.p).

FIG. 6 is a circuit diagram showing another embodiment of the level conversion circuit of the present invention. As shown in the figure, the level conversion circuit of this embodiment includes P-type MOS transistors TP23 and TP2.
2, TP23 and N-type MOS transistor TN22,
It is composed of TN22 and TN23. transistor T
P2 and TN23 constitute an inverter provided between the power supply VDD and the ground GND, and the input signal IN2 is supplied to its input. Also, the power supply V. 0 and ground GN
Transistors TP29, TP22 and TN
22 are connected in series, and the transistors TP22 and TN
The level-converted output 0UT2 is output from the connection point with 22 (signal line SL for outputting the output signal). Here, the transistor TN23 is provided between the connection point of the transistors TP23 and TP22 and the ground, and is connected to the gate of the transistor TN3.

An input signal IN2 is supplied. Further, the output of the inverter composed of transistors TP21 and TN22 is an inverted output 0tJT2, and the transistors TP23. It is supplied to gates 1 to 1 of TP22 and TN22.

Also in the embodiment shown in FIG. 6, when the input signal IN2 is at a high level "H", the transistor TP22 is switched off and the transistors TN21.7N23 are switched on. As a result, the inverted output 0UT2 is at a low level “L”.
'', the transistors TP22 and TP23 are switched on, and the transistor TN2 is switched off. Therefore, the signal line SL that takes out the output signal 0UT2 is connected to the on-resistance of the transistor TP23 and the transistor TN.
The output signal 0UT2 is at the level of the voltage divided by the on-resistance of the transistor TP22 in the on-state.
Output via . Conversely, when the input signal N2 is at a low level "L", the transistor TP22 is switched on and the transistors TN21 . TN23 is switched off. This causes an inverted output OUT.

becomes a high level "H", transistors TP22 and TP23 are switched off, and transistor TN22 is switched on.Therefore, the signal line SL from which the output signal 0UT2 is taken out is brought to the ground potential by the transistor TN22.

The level conversion circuit of this embodiment, like the level conversion circuit of FIG. 0UT2 can be obtained. Furthermore, unlike the level conversion circuit of FIG. 3 described above, the level conversion circuit of this embodiment has an output voltage level of the transistor Tp2S.
and TN23, and the on-resistances of transistors TP22 and TN22 are not affected by the output voltage level. Therefore, transistor TP22
And the on-resistance of TN22 can be changed freely,
The delay value of the level conversion circuit can be controlled.

FIG. 7 is a block diagram schematically showing a device to which the level conversion circuit of the present invention is applied, and in the figure, reference numerals B1,
B2, B is a level conversion circuit.

As shown in FIG. 7, for example, in response to the output of the 50V drive IC, the 5V drive IC1IOV drive IC and the
In an IC (level conversion IC) that converts a level to be suitable for a V drive IC, an input signal at a level of 50V is
The level conversion circuit Bl that converts the level of 50V to the level of IOV, the level conversion circuit B2 that converts the input signal of the 50V level to the level of IOV, and the level conversion circuit B3 that converts the input signal of the 50V level to the level of 20V, all of A single voltage power source (50V power source) is supplied. Therefore, unlike the level conversion IC shown in Fig. 9, the level conversion IC does not need to be provided with power supplies (5V power supply, 10■ power supply, and 20V terminals) corresponding to the respective output levels; Since only the terminals need to be provided, the number of pads within the level conversion IC can be minimized and the IC
The area occupied by the chip can be reduced.

FIG. 8 is a circuit diagram showing an embodiment of the delay circuit of the present invention.

The delay circuit of this embodiment is provided with the level conversion circuit of the example shown in FIG. 3, and when the voltage of the power supply Voo is supplied to its input terminal 16, the same voltage as the voltage of the power supply Va is obtained at its output terminal 17. , first-stage and second-stage inverters 131, r
sz is supplied with the same voltage as the voltage of the power source Va obtained at the output terminal 17 of the level converter circuit in the example in FIG. 3, and the final stage inverter hs is supplied with the voltage of the power source The rest of the structure is the same as the conventional example shown in FIG. 11.

According to the delay circuit of this embodiment, the same voltage as the voltage of the power supply Va is supplied as the power supply voltage to two inverters 131 and I32 among the inverters 131, 132 and hs connected in rows, Although the final stage inverter 133 is supplied with the voltage of the power supply ■DD, the level conversion circuit shown in the example in Fig. 3 is used, so when converting this into an IC, it is necessary to It is sufficient to provide an external terminal for the power source Va, and there is no need to provide an external terminal for the power source Va.

Therefore, according to the delay circuit of this embodiment, this
In order to reduce the number of pads on the IC chip,
The area occupied by the IC chip can be kept small.

Although the delay circuit of this embodiment is constructed using the level conversion circuit shown in the example shown in FIG. 3, it may alternatively be constructed using the level conversion circuit shown in the conventional example shown in FIG. In this case as well, the same effects as described above can be obtained.

[Effects of the Invention] As detailed above, the level conversion circuit according to the present invention uses a single power supply to obtain an output signal converted to an arbitrary voltage. In this case, the area occupied by the IC chip can be kept small by minimizing the number of pads on the IC chip.

Furthermore, although the delay circuit according to the present invention requires two types of power supply voltages, since it uses the level conversion circuit according to the present invention, when converting it into an IC, it is difficult to use the power supply voltage. Since it is sufficient to provide one external terminal as an external terminal, when this is integrated into an IC, the number of pads on the IC chip can be reduced and the area occupied by the IC chip can be kept small.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the principle of a level conversion circuit according to the present invention, FIG. 2 is a circuit diagram showing the principle of a delay circuit according to the present invention, and FIG. 3 is an embodiment of the level conversion circuit according to the present invention. 4 and 5 are equivalent circuit diagrams for explaining the operation of the level conversion circuit of FIG. 3, and FIG. 6 is a circuit diagram showing another embodiment of the level conversion circuit of the present invention. FIG. 7 is a block diagram schematically showing a device to which the level conversion circuit of the present invention is applied, FIG. 8 is a circuit diagram showing an embodiment of the delay circuit according to the present invention, and FIG. 9 is a conventional level conversion circuit. FIG. 10 is a block diagram schematically showing a device to which a conventional level conversion circuit is applied; FIG. 11 is a circuit diagram showing a conventional delay circuit. GND...Ground IN, IN2...Input signal OUT+, 0UT2...Output signal SL...Signal line TN for taking out the output signal,...TN12/TN. TN23, TN223TN23...N type MO3) Landisk TPI1. TP12 TP22, TP22, TP23...P-type MO3 transistor V00...Power supply Va...Power supply, -1-fB: 45
--"-m A circuit diagram showing the principle of a level conversion circuit according to the present invention. FIG. FIG. 3 is a circuit diagram showing an embodiment of the present invention; FIG. 3 is an equivalent circuit diagram for explaining the operation of the level conversion circuit shown in FIG. 3; FIG. 5 is an equivalent circuit diagram for explaining the operation of the level conversion circuit shown in FIG. Circuit 1 showing another embodiment of the level conversion circuit 6
Group 11 h2133 An embodiment of a delay circuit according to the present invention FIG. 9 is a circuit diagram showing an example of a conventional level conversion circuit.

Claims (1)

[Claims] 1. A level conversion circuit that converts the level of an input signal (IN_1) and extracts an output signal (OUT_1) of a predetermined level, the circuit comprising an inverter (to which the input signal (IN_1) is supplied)
I) and a signal line (SL) that takes out the output signal (OUT_1)
and a power supply (V_D_D), the first one of one conductivity type having its gate supplied with the output of the inverter (I).
MOS transistor (TP_1_2), and the first MO, which is provided between the signal line (SL) and the ground (GND) and whose gate is supplied with the input signal (IN_1).
A second MOS transistor (TN_1_2) of the opposite conductivity type to the S transistor (TP_1_2) and the signal line (
a third MOS transistor (TN_1_3) of an opposite conductivity type, which is provided between the input signal (IN_1) and the ground (GND) and whose gate is supplied with the output of the inverter (I); With the first and second MOS transistors (TP_1_2, TN_1_2) both in the on state, the voltage of the power supply (V_D_D) is determined by the ratio of the on-resistances of the first and second MOS transistors (TP_1_2, TN_1_2). A level conversion circuit characterized in that the output signal (OUT_1) is taken out at an arbitrary voltage lower than . 2. A level conversion circuit that converts the level of an input signal (IN_2) and extracts an output signal (OUT_2) of a predetermined level, the inverter () to which the input signal (IN_2) is supplied.
I) and a signal line (SL) that takes out the output signal (OUT_2)
and a power supply (V_D_D) connected in series,
first and fourth MOS transistors (of one conductivity type) each having a gate supplied with the output of the inverter (I);
TP_2_2, TP_2_3) and the first and fourth MOS transistors (TP_2_2, TP_2_3) are connected in series between the ground (GND) and the input signal (TP_2_2, TP_2_3) is connected to the gate.
A second MOS transistor (TN_2_3) of the opposite conductivity type to the first MOS transistor (TP_2_2) to which IN_2) is supplied, and a second MOS transistor (TN_2_3) provided between the signal line (SL) and the ground (GND) and connected to the gate. A third MOS transistor (TN_2_2) of the opposite conductivity type is supplied with the output of the inverter (I).
), the first, second and fourth MOS transistors (TP_2_2, TN_2_
3, TP_2_3) are all turned on and the first and second MOS transistors (TP_2_2, TN_2
The on-resistance ratio of the power source (V_D_D
) of any voltage lower than the voltage of the output signal (OUT
_2) and the fourth transistor (T
The output signal (OUT_
2) A level conversion circuit characterized in that a delay value is defined. 3. Multiple inverters connected in series (I_3_1
, I_3_2, I_3_3) and the level conversion circuit according to claim 1 or 2, and the plurality of inverters (
Inverters (I_3_1, I_3_1, I_3_2, I_3_3) other than the final stage inverter (I_3_3)
, I_3_2) is connected to the input terminal (1) of the level conversion circuit according to claim 1 or 2.
4), when the first voltage is supplied to the output terminal (15
) is supplied as a power supply voltage, and the first voltage is supplied as a power supply voltage to inverters other than the at least one inverter. circuit.