JP2544815B2 - Level shift circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a level shift circuit for converting an input voltage of a certain voltage system into a voltage level of another voltage system and outputting the voltage level.

[Conventional technology]

FIG. 3 is a circuit diagram showing an example of a conventional level shift circuit having a C-MOS structure.

In the figure, the voltage level input to input terminal 1 is 0V.
The first-stage circuit section A that receives an input voltage of up to + 5V is formed by connecting _two inverters a ₁ and a ₂ in cascade. That is,
The inverter a _{1 in the} preceding stage connects the drain of the P-channel transistor Q _{1 and} the drain of the N-channel transistor Q ₂ while the source of the P-channel transistor Q ₁ is connected to the high potential (+ 5V) power supply 2 and the source of the N-channel transistor Q ₂ is connected. Connect the sources to the ground, that is, to the low potential (0V) power source 3,
Channel transistor Q ₁ and N channel transistor
It is configured by connecting the gate of Q ₂ to input terminal 1, and the drain of P-channel transistor Q ₁ and N-channel transistor.
The connection point with the drain of Q ₂ is the output terminal of this inverter a ₁ . Similarly, in the latter-stage inverter a ₂ as well, the drain of the P-channel transistor Q _{3 and} the drain of the N-channel transistor Q ₄ are connected, while the source of the P-channel transistor Q ₃ is connected to the high potential (+ 5V) power source 2
The low potential (0V) of the source of the N-channel transistor Q _4.
Each of them is connected to the power supply 3 and the gates of the P-channel transistor Q ₃ and the N-channel transistor Q ₄ are connected to the output terminal of the inverter a _{1 in} the preceding stage, and the drain of the P-channel transistor Q ₃ and the N-channel transistor Q ₄ are connected. The connection point with the drain is the output terminal of this inverter a ₂ .

The next-stage circuit section B also includes two inverters b ₁ and b ₂ , and one inverter b ₁ connects one P-channel transistor Q ₅ and two N-channel transistors Q ₆ and Q ₇ in series, and the other one. Inverter b _{2 is} also constructed by connecting one P-channel transistor Q ₈ and two N-channel transistors Q ₉ and Q ₁₀ in series.

That is, the inverter b ₁ is connected to the P-channel transistor Q ₅
The drain and the drain is connected to N-channel transistors Q _6, N-channel while connecting the drain of the source and the N-channel transistor Q ₇ of the transistor Q _6, P source of high potential of the channel transistor Q ₅ (+ 5V) Power Two
The source of the N-channel transistor Q ₇ at low potential (-10
V) P-channel transistor Q connected to power supply 4 respectively
₅ and N output terminals of the inverter a ₁ to the gate described above channel transistor Q _6, also formed by connecting to the output terminal of the inverter b ₂ to be described later gates of N-channel transistors Q _7, P-channel transistor Q ₅ connection point of the drain of the drain and N-channel transistor Q ₆ is an output terminal of the inverter b _1. Also,
Similarly, for the other inverter b ₂ , the drain of the P-channel transistor Q ₈ and the N-channel transistor Q ₉
The source of the N-channel transistor Q _{9 and} the drain of the N-channel transistor Q ₁₀ are connected to each other, while the source of the P-channel transistor Q ₈ is connected to the high potential (+ 5V) power supply 2 and the N-channel transistor Q ₁₀ is connected to the source of the N-channel transistor Q _10. Of the P channel transistor Q ₈ and the N channel transistor Q ₉ are connected to the output terminal of the inverter a ₂ described above, and the gate of the N channel transistor Q ₁₀ is connected to the low potential (−10V) power source 4. Inverter b
Is constructed by connecting the respective _first output terminal, the drain and the N-channel transistor connection point between the drain of Q ₉ is N inverter b ₁ as described above the P-channel transistor Q ₈ is an output terminal of the inverter b ₂ Connected to the gate of channel transistor Q ₇ .

 Next, the operation of the level shift circuit will be described.

If the signal input to the input terminal 1 is at the L level (= 0V), P-channel transistors to Q ₁ inverter a ₁ in the first-stage circuit A is turned on, the N-channel transistor Q ₂ is turned off, the inverter a ₁ Output of H level (+
5V). At this time, since the P-channel transistor Q ₃ of the next-stage inverter a ₂ is turned off and the N-channel transistor Q ₄ is turned on, the output of this inverter a ₂ is at L level (
0V).

Further, since the P-channel transistor Q ₈ of the inverter b ₂ in the next-stage circuit section B is turned on, this inverter b ₂
Output becomes H level (+ 5V). Therefore, the gate of the N channel transistor Q ₇ of the inverter b ₁ becomes H level, and the N channel transistor Q ₇ is turned on. On the other hand, the P-channel transistor of this inverter b ₁
The H level signal from the inverter a ₁ is applied to the gates of Q ₅ and the N channel transistor Q ₆ , so that the P channel transistor Q ₅ is turned off and the N channel transistor Q ₆ is turned on. Accordingly, the output of the inverter b ₁ becomes L level (-10 V). This output is the logic circuit G1 (see FIG. 4) provided in the next stage of the level shift circuit S1.
Given to.

Next, the signal input to the input terminal 1 is at H level (= +
In the case of 5V), all the logics of the above-mentioned operation are inverted, and the output terminal of the next stage circuit section B, that is, the inverter b ₁
An output of H level (+ 5V) is obtained at the output terminal of.
That is, an output voltage of -10V to + 5V can be obtained for an input voltage of 0V to + 5V.

[Problems to be Solved by the Invention]

Since the conventional level shift circuit is configured as described above, only one of the high and low potentials of the input voltage can be level-shifted. That is, either the high potential or the low potential becomes the same as the voltage level at the time of input.

Therefore, when converting an input voltage of 0V to + 5V into, for example, a voltage of ± 10V, a semiconductor integrated circuit IC including the level shift circuit S1 and the logic circuit G1 described above as shown in FIG.
Output voltage from -10V to + 5V taken from 1
IC level shift circuit S2 (+ 10V high potential power supply 5 and -10V
(Which is connected to the low-potential power source 4 in FIG. 2), the level shift must be performed by two ICs in two steps, and the process becomes complicated.

The present invention has been made in order to solve such a problem, and is a level shifter capable of shifting both a high potential level and a low potential level of an input voltage by a monolithic circuit in a one-chip IC. Aim to get the circuit.

[Means for solving the problem]

A level shift circuit according to the present invention includes an inverter connected to a first high potential power supply and a first low potential power supply, and sets a voltage level of the first high potential power supply to an H level in response to an input signal. A first-stage circuit unit that obtains an output voltage that sets the voltage level of the first low-potential power supply to the L level, and a second low-potential power supply that is lower than the voltage levels of the first high-potential power supply and the first low-potential power supply. An output voltage having a logic inverse to that of the input signal in response to the output voltage of the first-stage circuit section, including the connected inverter, and setting the voltage level of the first high-potential power supply to the H level to the voltage of the second low-potential power supply. A first middle-stage circuit section for obtaining an output voltage whose level is L level; and an inverter connected to the second high-potential power supply and the first low-potential power supply which are higher than the voltage level of the first high-potential power supply. Including, input signal in response to the output voltage of the first-stage circuit A second middle-stage circuit section for obtaining an output voltage of an inverse logic, the output voltage of which the voltage level of the second high-potential power supply is H level and the voltage level of the first low-potential power supply is L level; Output of the same logic as the input signal in response to the output voltage of the first middle-stage circuit section and the output voltage of the second middle-stage circuit section. A one-chip semiconductor integrated circuit, which includes a final-stage circuit section that obtains an output voltage that is a voltage and that sets the voltage level of the second high-potential power supply to the H level and the voltage level of the second low-potential power supply to the L level. It is composed monolithically.

[Action]

According to the present invention, in a one-chip semiconductor integrated circuit, an output voltage in which the voltage level of the first high-potential power supply is H level and the voltage level of the first low-potential power supply is L level in response to an input signal is the first stage. In response to the output voltage obtained by the circuit section, in the first middle-stage circuit section, an output voltage that sets the voltage level of the first high-potential power supply to the H level and the voltage level of the second low-potential power supply to the L level In response to the output voltage of the input signal, the output voltage of the logic opposite to that of the input signal is obtained, and in response to the output voltage of the first-stage circuit unit, the voltage level of the second high-potential power supply is at the H level and the first low potential in the second middle-stage circuit unit. An output voltage that sets the voltage level of the power supply to the L level and has an inverse logic to the input signal is obtained, and further, in response to the output voltage of the first and second middle stage circuit units, the second stage of the final stage circuit unit responds. Voltage level of the high potential power source of H level, The voltage level of the voltage source and the L-level (i.e. H level, which is level shifted with L-level) the output voltage of the input signal the same logic is obtained an output voltage.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the level shift circuit according to the present invention.

In FIG. 1, the structure of the first-stage circuit section A that receives a signal with a voltage level of 0V to + 5V input to the input terminal 1 is the same as that of the conventional circuit shown in FIG. 3, and the structure of the first middle-stage circuit section B1. Also, except for the position of the output terminal, it is the same as the next-stage circuit section B in the conventional circuit. Here, the front-stage inverter and the rear-stage inverter of the first middle-stage circuit unit B1 are indicated by reference numerals b ₁₁ and b ₁₂ , respectively.

The second middle circuit section B2 has the same structure as the first middle circuit section B1.
One of an inverter b _21, b _22, one inverter b ₂₁
Connects two P-channel transistors Q ₁₁ , Q ₁₂ and one N-channel transistor Q ₁₃ in series, and the other inverter b ₂₂ also has two P-channel transistors Q ₁₄ , Q ₁₅
And one N-channel transistor Q ₁₆ are connected in series.

That is, the inverter b ₂₁ are P-channel transistor Q
Connect ₁₁ and the source of the drain and the P-channel transistor Q _12, the drain of the P-channel transistor Q ₁₂ and N
While connecting the drain channel transistor Q _13, P-channel source to a second high potential (+ 10V) power source 5 of the transistor Q _11, N-channel source a first low potential of the transistor Q ₁₃ (0V) power supply 3 To P,
The gate of the channel transistor Q _{11 is used} as the output terminal of the inverter b ₂₂ described later, and the gates of the P-channel transistor Q ₁₂ and the N-channel transistor Q ₁₃ are used as the inverter a.
₁ is connected to the output terminal respectively, and the drain of the P-channel transistor Q ₁₂ and the N-channel transistor Q ₁₂ are connected.
The connection point with the drain of ₁₃ is the output terminal of this inverter b ₂₁ . Similarly, for the other inverter b ₂₂ , the drain of the P-channel transistor Q ₁₄ and the source of the P-channel transistor Q ₁₅ are connected, and P
The drain of the channel transistor Q _{15 and} the drain of the N-channel transistor Q ₁₆ are connected, while the source of the P-channel transistor Q ₁₄ is the second high potential (+ 10V) power supply 5 and the source of the N-channel transistor Q ₁₆ is the first. Connected to the low potential (0V) power source 3 of the inverter a ₂ , the gate of the P-channel transistor Q ₁₄ to the output terminal of the above-mentioned inverter b ₂₁ , and the gates of the P-channel transistor Q ₁₅ and the N-channel transistor Q ₁₆ to the inverter a ₂ . The drain of the P-channel transistor Q ₁₅ , which is the output terminal of the inverter b ₂₂ , and the N
As described above, the connection point with the drain of the channel transistor Q ₁₆ is the P-channel transistor Q ₁₁ of the inverter b _21.
Connected to the gate.

The first final stage circuit section C1 is a P-channel transistor
It consists of an inverter in which Q ₁₇ and two N-channel transistors Q ₁₈ and Q ₁₉ are connected in series. That is, the final stage circuit unit C1 connects the drain of the P-channel transistor Q _{17 and} the drain of the N-channel transistor Q ₁₈ , and the source of the N-channel transistor Q ₁₈ and the N-channel transistor Q ₁₈ are connected.
The source of the P-channel transistor Q ₁₇ is connected to the second high potential (+10 V) power source 5, and the source of the N-channel transistor Q ₁₉ is connected to the second low potential (−10 V) while connecting to the drain of _19.
V) P-channel transistor Q connected to power supply 4 respectively
The gates of ₁₇ and N-channel transistor Q ₁₈ are connected to the output terminal of inverter b ₂₂ described above, and the gate of N-channel transistor Q ₁₉ is connected to the output terminal of inverter b ₁₂ described above.
The connection point between the drain of Q _{17 and} the drain of the N-channel transistor Q ₁₈ is the output terminal of the final stage circuit section C 1.

The second last-stage circuit C2 is made two P-channel transistors Q _20, Q ₂₁ and one N-channel transistor Q ₂₂ from the inverter connected in series. That is, the final stage circuit section C2 connects the drain of the P-channel transistor Q ₂₀ and the source of the P-channel transistor Q ₂₁ to each other, and
The drain of the channel transistor Q _{21 and} the drain of the N-channel transistor Q ₂₂ are connected, while the source of the P-channel transistor Q ₂₀ is used as the second high potential (+10 V) power source 5 and the source of the N-channel transistor Q ₂₂ is used as the second source. Connected to the low-potential (-10V) power source 4 of the above-mentioned inverter, the gate of the P-channel transistor Q ₂₀ to the output terminal of the above-mentioned inverter b ₂₂ , and the gates of the P-channel transistor Q ₂₁ and the N-channel transistor Q ₂₂ to the above-mentioned inverter. b ₁₂
Of the P-channel transistor Q ₂₁ and the N-channel transistor Q _22.
The connection point with the drain of is the output terminal of this final stage circuit section C2.

FIG. 2 shows the above-described level shift circuit S3 and the logic circuit G2 provided at the next stage thereof in one semiconductor integrated circuit IC.
FIG. 3 is a block diagram showing a configuration incorporated in 2.

Next, the operation of the level shift circuit S3 will be described.

If the signal input to the input terminal 1 is at the L level (= 0V), P-channel transistors to Q ₁ inverter a ₁ in the first-stage circuit A is turned on, the N-channel transistor Q ₂ is turned off, the inverter a ₁ Output of H level (+
5V), the P-channel transistor Q ₃ of the next-stage inverter a ₂ is turned off, and the N-channel transistor Q ₄ is turned on, so that the output of this inverter a ₂ becomes L level (0V).

Further, at this time, in the first middle circuit section B1, the P-channel transistor Q ₅ of the front-stage inverter b ₁₁ is turned off, the N-channel transistor Q ₆ is turned on, and the rear-stage inverter b ₁₂ is turned on.
P-channel transistor Q ₈ turns on and N-channel transistor Q ₉ turns off. As a result, the output of the inverter b ₁₂ is H-level (+ 5V) becomes, N-channel transistor Q ₇ of the inverter b ₁₁ is turned on, the inverter
The output of b ₁₁ is L level (-10 V).

On the other hand, in the second middle-stage circuit section B2, the inverter b ₂₁
The P-channel transistor Q ₁₂ is turned off, N-channel transistor Q ₁₃ is turned on, the output of the inverter b ₂₁ is L level (0V). In addition, the inverter b
The P channel transistors Q ₁₄ and Q ₁₅ of ₂₂ are turned on, the N channel transistor Q ₁₆ is turned off, and the output of the inverter b ₂₂ thereof becomes H level (+10 V).

At this time, P-channel transistor Q ₁₇ in the first end stage circuit unit C1 is off, N-channel transistors Q _18, Q ₁₉ is turned on, its output is at the L level (-10 V). This output is given to the logic circuit G2 (FIG. 2) provided in the next stage.

The second last-stage circuit C2 in the P-channel transistors Q _20, Q ₂₁ is turned off, N-channel transistor Q ₂₂ is turned on, the output is also L level (-10 V). This output is also given to the logic circuit G2 (FIG. 2) provided in the next stage.

Next, the signal input to the input terminal 1 is at H level (= + 5
In the case of V), all the logics of the above-mentioned operation are inverted, and the inverter b _{12 in} the latter stage of the first middle stage circuit unit B1
From the output of the L level (-10 V) is taken, the output of the L level (0V) is fetched from the second downstream inverters b ₂₂ of the middle circuit portion B2. Accordingly, P-channel transistor Q ₁₇ in the first end stage circuit portion C1 is turned on, N
The channel transistors Q ₁₈ and Q ₁₉ are turned off, and an H level (+10 V) output is taken out. Second final stage circuit section C
In the case of 2, the P-channel transistors Q ₂₀ and Q ₂₁ are turned on and the N-channel transistor Q ₂₂ is turned off.
The output of + 10V) is taken out.

In this way, for the input voltage of 0V to + 5V, the output voltage of -10V to + 10V with the voltage level shifted for both high and low potentials can be obtained. That is, for example, the second
As shown in the figure, in the case of the semiconductor integrated circuit IC2 in which the level shift circuit S3 having the above configuration is provided in the preceding stage of the logic circuit G2, the input voltage of 0V to + 5V input from the input terminal 1 is -10V at the level shift circuit S3. ~ + 10V, processed by logic circuit G2 and output as -10V ~ + 10V signal Output terminal 6
Will be taken from.

〔The invention's effect〕

As described above, according to the present invention, both the high potential level and the low potential level of the input voltage can be shifted to different voltage levels by the monolithic circuit in the IC of one chip. Since it is unnecessary to add another level shift circuit for the level shift of (1), there is an effect that the logic circuit system can be constructed at low cost.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a level shift circuit according to the present invention, FIG. 2 is a block diagram showing a configuration in which the level shift circuit is combined with another logic circuit, and FIG.
FIG. 4 is a circuit diagram showing a conventional level shift circuit, and FIG. 4 is a block diagram showing a configuration in which the level shift circuit is combined with another logic circuit and another level shift circuit. In the figure, 1 is an input terminal, 2 is a first high-potential power supply, 3
Is a first low potential power source, 4 is a second low potential power source, 5 is a second
High-potential power source, A is the first stage circuit part, B1 is the first middle stage circuit part, B2 is the second middle stage circuit part, C1 is the first final stage circuit part, and C2 is
Is a second final stage circuit unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. An inverter connected to a first high-potential power supply and a first low-potential power supply, wherein the voltage level of the first high-potential power supply is set to H level in response to an input signal.
A first-stage circuit section that obtains an output voltage that sets the voltage level of the low-potential power supply to L level, and a second low-potential power supply that is lower than the voltage level of the first high-potential power supply. An output voltage having an inverse logic to the input signal in response to the output voltage of the first-stage circuit unit, the voltage level of the first high-potential power supply being H level, and the second low voltage. A first middle-stage circuit section for obtaining an output voltage for setting the voltage level of the potential power supply to the L level; a second high potential power supply higher than the voltage level of the first high potential power supply; and the first low potential power supply An inverter connected to the first stage circuit section, which has an output voltage of an inverse logic to the input signal in response to the output voltage of the first-stage circuit section, and sets the voltage level of the second high-potential power supply to the H level. Output that sets the voltage level of the low-potential power supply to L level A second middle-stage circuit section for obtaining a voltage; and an inverter connected to the second high-potential power supply and the second low-potential power supply, wherein the output voltage of the first middle-stage circuit section and the second In response to the output voltage of the middle circuit section, the output voltage has the same logic as the input signal, the voltage level of the second high-potential power supply is H level, and the voltage level of the second low-potential power supply is L level. A level shift circuit monolithically integrated into a one-chip semiconductor integrated circuit, which includes a final stage circuit section for obtaining an output voltage.